Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 374

External Signals
12.7 Signal States During Reset
During a reset, the MPC885 signals behave as shown in
Reset Signal
HRESET or PORESET Bus signals are high impedance.
SRESET
12-44
Table 12-5. General Signal Behavior During Reset
Port I/O signals are configured as inputs and are, therefore, high impedance.
Memory controller signals are driven to their inactive state. Refresh stops.
(For the behavior of specific signals during a hard reset, see
"MPC885/MPC880 System Bus
The current bus cycle aborts. Bus signals revert to their inactive state. (For example, BR or
BG negate, and address and data signals become high impedance.)
Memory controller aborts the current access, and signals drive to their inactive state (high).
Refresh continues.
Port I/O signals are not reconfigured (maintain previous programming).
SIU pin configuration maintains previous programming; see
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Table 12-5.
Signal Behavior
Section 12.1.2,
Signals.")
Table 12-3.
Freescale Semiconductor