Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 723

Powerquicc family

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SCC Asynchronous HDLC Mode and IrDA

Asynchronous HDLC and IrDA uses HDLC framing techniques with UART-type characters. This

document refers to both protocols collectively as asynchronous HDLC. The asynchronous HDLC protocol

is typically used as the physical layer for point-to-point protocol (PPP) and the infrared link access

protocol (IrLAP). Although asynchronous HDLC can be implemented in conjunction with the core, it is

more efficient and less computationally-intensive to let the CPM handle framing and transparency

functions. Additional hardware features to support infrared encoding/decoding are described in

Section 25.18, "IrDA Encoder/Decoder (SCC2 Only)."

The RFC 1549 octet stuffing/unstuffing provided by this mode supports only asynchronous transmission.

This mode cannot be used to provide octet stuffing for synchronous communication lines.

Asynchronous HDLC Features

The following list summarizes the main features of the SCC in asynchronous HDLC mode:

Flexible buffer structure lets all or part of a frame be sent or received

Separate interrupts for received frames and transmitted buffers

Automatic CRC generation and checking

Support for nonmultiplexed serial interface control signals

Automatic generation of opening and closing flags

Reception of frames with a single shared flag

Automatic generation and stripping of transparency characters according to RFC 1549 using

transmit and receive control character maps

Programmable opening flag, closing flag, and control escape characters

Automatic transmission of the abort sequence after a

Automatic transmission of idle characters between frames and between characters

Asynchronous HDLC Frame Transmission Processing

The SCC in asynchronous HDLC mode (asynchronous HDLC controller) works with minimal core

intervention. When the core enables the transmitter and sets TxBD[R] in the first BD of the table, the

asynchronous HDLC controller fetches data from memory and starts sending the frame. If the current

TxBD[L] is set (last buffer of a frame), the CRC and closing flag are appended. If TxBD[CM] is zero, the

transmitter updates frame status bits in the BD and clears TxBD[R]. If TxBD[I] is set, the controller sets

SCCE[TXB] so an interrupt can be generated after each buffer, after a group of buffers, or after each frame

Freescale Semiconductor

MPC885 PowerQUICC Family Reference Manual, Rev. 2

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