Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 921

Powerquicc family

Table of Contents

PAPAR[DD n ] = 0

(General I/O)

Clearing the corresponding PADIR bit makes the signal an input; setting PADIR makes it an output.

Multi-function peripheral input signals, such as CLK1/TIN1/L1RCLKA, can perform multiple functions simultaneously.

(That is, a clock supplied at PA7 can be used for both CLK1 and TIN1.)

Port A signals selected for general-purpose I/O can be accessed through the port A data register (PADAT).

Data written to PADAT is stored in an output latch. For port A outputs, the latch data is gated onto the

signal. When PADAT is read, the signal itself is read. For inputs, data written to PADAT is also stored in

the output latch but cannot reach the port signal, so when PADAT is read, the signal's state is read. If an

input to a peripheral is not supplied from a signal, the default value listed in

Port A Registers

Port A has four memory-mapped control registers, described in the following sections.

Port A Open-Drain Register (PAODR)

The port A open-drain register (PAODR), shown in

channel output capability are configured in a normal or wired-OR configuration. Setting the PAODR bits

configure the signals for open-drain operation.

Freescale Semiconductor

Table 34-1. Port A Pin Assignment (continued)

PAPAR[DD n ] = 1

PADIR[DR n ] = 0

CLK1/TIN1/L1RCLKA

CLK3/TIN2/L1TCLKA

RMII1-CRS_DV

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Pin Function

Input to On-Chip Peripherals

PADIR[DR n ] = 1

CLK1/TIN1/L1RCLKA = BRGO1

CLK3/TIN2/L1TCLKA = BRGO2

34-1, determines which port signals with serial

Parallel I/O Ports

L1RXDA = GND

is supplied.