Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 758

SCC Ethernet Mode
and total frame length to 1,518 bytes. The last 4 bytes of the frame are the frame check sequence (FCS), a
standard 32-bit CCITT-CRC polynomial used in many protocols.
When a station needs to transmit, it checks for LAN activity. When the LAN is silent for a specified period,
the station starts sending. At that time, the station continually checks for collisions on the LAN; if one is
found, the station forces a jam pattern (all ones) on its frame and stops sending. Most collisions occur close
to the beginning of a frame. The station waits a random period of time, called a backoff, before trying to
retransmit. Once the backoff time expires, the station waits for silence on the LAN before retransmitting,
which is called a retry. If the frame cannot be sent within 15 retries, an error occurs.
10-Mbps ethernet transmits at 0.8 µs per byte. The preamble plus start frame delimiter is sent in 6.4 µs.
The minimum 10-Mbps ethernet interframe gap is 9.6 µs and the slot time is 52 µs.
27.1 Ethernet on the MPC885
Setting GSMR[MODE] to 0b1100 selects ethernet. The SCC performs the full set of IEEE 802.3/ethernet
CSMA/CD media access control and channel interface functions.
diagram.
U-BUS
PERIPHERAL BUS
REJECT
RSTRT
CD = RENA
CTS = CLSN
RXD
The MPC885 ethernet controller requires an external serial interface adaptor (SIA) and transceiver
function to complete the interface to the media. This function is implemented in the Motorola MC68160
enhanced ethernet serial transceiver (EEST).
The MPC885 and EEST solution provides a direct connection to the attachment unit interface (AUI) or
twisted-pair (10BASE-T). The EEST provides a glueless interface to the MPC885, Manchester encoding
and decoding, automatic selection of 10BASE-T versus AUI ports, 10BASE-T polarity detection and
correction. The MC68160 documentation gives more information.
27-2
CONTROL
REGISTERS
RX
RECEIVER
CONTROL
DATA
UNIT FIFO
SHIFTER
Figure 27-2. Ethernet Block Diagram
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Figure 27-2
SLOT TIME
AND DEFER
GENERATOR
INTERNAL CLOCKS
TX
TRANSMITTER
DATA CONTROL
FIFO UNIT
TXD
SHIFTER
shows the ethernet block
COUNTER
RCLK
CLOCK
TCLK
RTS = TENA
CD = RENA
CTS = CLSN
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