Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 830

Serial Management Controllers (SMCs)
0
Field
Reset
R/W
Address
Figure 29-20. SMC GCI Event Register (SMCE)/Mask Register (SMCM)
Table 29-23 describes SMCE/SMCM fields.
Bits Name
0–3 — Reserved, should be cleared.
4 CTXB C/I channel buffer transmitted. Set when the C/I transmit buffer becomes empty.
5 CRXB C/I channel buffer received. Set when the C/I receive buffer becomes full.
6 MTXB Monitor channel buffer transmitted. Set when the monitor transmit buffer becomes empty.
7 MRXB Monitor channel buffer received. Set when the monitor receive buffer becomes full.
29-36
3
—
0xA86 (SMCE1), 0xA96 (SMCE2)/ 0xA8A (SMCM1), 0xA9A (SMCM2)
Table 29-23. SMCE/SMCM Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
4 5
CTXB CRXB
0000_0000
R/W
Description
6 7
MTXB MRXB
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