Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 248

Powerquicc family

Table of Contents

Memory Management Unit

MSR[PR] M_CASID[CASID] 32-Bit EA

32-Entry Fully Associative TLB

32-Bit Physical Address

Figure 8-3. Effective-to-Physical Address Translation for 4-Kbyte Pages Block Diagram

A TLB hit occurs if the incoming EA matches the EPN and M_CASID[CASID] matches the ASID field

in a valid TLB entry, and if the subpage validity flag is set for the subpage that the incoming EA points to.

If a hit is detected, the contents of the physical page number are concatenated with the appropriate number

of lsbs from the EA to form the physical address sent to the cache and memory system.

Using Access Protection Groups

Access control is assigned on a page-by-page basis; additional control is provided on a protection group

basis. Each TLB entry holds an access protection group (APG) number. When a match is detected, the

value of the matched entry's APG is used to index a field in the access protection register (MI_AP or

MD_AP) that defines access control for the translation. Each Mx_AP contains 16 fields. The field content

is used according to the group protection mode.

To be consistent with the PowerPC OEA, the APG value should match the four msbs of the effective page

number. To override protection using APG, use it on blocks of addresses which are defined by the 4 msbs

of the effective page number. If APG is not to be used for a particular block, set the GP for that block to

'client' in the Mx_AP register. To ignore it globally, set all of the Mx_AP fields to 01. In default mode,

each field holds the Kp and Ks bits for the corresponding segment defined by the level-one table descriptor.

In domain manager mode, each field holds override information over the page protection setting: no

override, no access override, and free access override.

Physical Page Number

MPC885 PowerQUICC Family Reference Manual, Rev. 2

32-Bit Logical

Page Protection

Group Number

Lookup Table

Implementation-

Specific TLB

Miss Exceptions

Implementation-

Error Exceptions

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