Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 711

3. Configure port A to enable CLK3. Set PAPAR[5] and clear PADIR[5].
4. Connect CLK3 to SCC2 using the SI. Write 0b110 to SICR[R2CS] and SICR[T2CS].
5. Connect the SCC2 to the NMSI (its own set of pins) and clear SICR[SC2].
6. Write 0x0001 to the SDCR to initialize the SDMA configuration register.
7. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RxBD and TxBD tables in
dual-port RAM. Assuming one RxBD at the start of dual-port RAM and one TxBD following it,
write RBASE with 0x0000 and TBASE with 0x0008.
8. Write 0x0041 to CPCR to execute the
updates RBPTR and TBPTR of the serial channel with the new values of RBASE and TBASE.
9. Write RFCR with 0x10 and TFCR with 0x10 for normal operation.
10. Write MRBLR with the maximum number of bytes per Rx buffer. Choose 256 bytes (MRBLR =
0x0100) so an entire Rx frame can fit in one buffer.
11. Write C_MASK with 0x0000F0B8 to comply with 16-bit CCITT-CRC.
12. Write C_PRES with 0x0000FFFF to comply with 16-bit CCITT-CRC.
13. Clear DISFC, CRCEC, ABTSC, NMARC, and RETRC for clarity.
14. Write MFLR with 0x0100 so the maximum frame size is 256 bytes.
15. Write RFTHR with 0x0001 to allow interrupts after each frame.
16. Write HMASK with 0x0000 to allow all addresses to be recognized.
17. Clear HADDR1–HADDR4 for clarity.
18. Initialize the RxBD. Assume the buffer is at 0x0000_1000 in main memory. RxBD[Status and
Control]= 0xB000, RxBD[Data Length] = 0x0000 (not required), and RxBD[Buffer Pointer] =
0x0000_1000.
19. Initialize the TxBD. Assume the Tx data frame is at 0x0000_2000 in main memory and contains
five 8-bit characters. TxBD[Status and Control] = 0xBC00, TxBD[Data Length] = 0x0005, and
TxBD[Buffer Pointer] = 0x0000_2000.
20. Write 0xFFFF to SCCE to clear any previous events.
21. Write 0x001A to SCCM to allow TXE, RXF, and TXB interrupts.
22. Write 0x2000_0000 to the CPM interrupt mask register (CIMR) to allow SCC2 to generate a
system interrupt. The CICR should also be initialized.
23. Write 0x0000_0000 to GSMR_H2 to enable normal CTS and CD behavior with idles (not flags)
between frames.
24. Write 0x0000_0000 to GSMR_L2 to configure CTS and CD to control transmission and reception
in HDLC mode. Normal Tx clock operation is used. Notice that the transmitter (ENT) and receiver
(ENR) have not been enabled. If inverted HDLC operation is preferred, set RINV and TINV.
25. Write 0x0000 to PSMR2 to configure one opening and one closing flag, 16-bit CCITT-CRC, and
prevent multiple frames in the FIFO.
26. Write 0x00000030 to GSMR_L2 to enable the transmitter and receiver. This additional write
ensures that ENT and ENR are enabled last.
Freescale Semiconductor
INIT RX AND TX PARAMS
MPC885 PowerQUICC Family Reference Manual, Rev. 2
SCC HDLC Mode
command for SCC2. This command
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