Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 396

External Bus Interface
CLKOUT
BR
BG
BB
A[0:31], AT[0:3]
R/W
TSIZ[0:1]
BURST
TS
BDIP
Data
TA
Figure 13-17. Burst-Write Cycle: 32-Bit Port Size, Zero Wait States
Figure 13-18 shows an attempted burst read to a slave device that does not support bursting. The slave
acknowledges the first transfer and also asserts the burst-inhibit signal (BI). The MPC885 responds by
terminating the burst and accessing the rest of the 16-byte block, using three single-beat read cycles.
13-22
MPC885 PowerQUICC Family Reference Manual, Rev. 2
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Will drive another data
Data is Data is Data is
sampled sampled sampled
Last beat
Data is
sampled
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