Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 100

MPC885 Overview
1.1 Features
The following list summarizes the key MPC885 family features:
• Embedded MPC8xx core up to 120 MHz. The 120-MHz core frequency supports the 2:1 mode
only.
• Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode)
• The available core frequencies are 66, 80, and 120 MHz.
• Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two
32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution
— 8-Kbyte data cache and 8-Kbyte instruction cache (see
– Instruction cache is two-way, set-associative with 256 sets in two blocks.
– Data cache is two-way, set-associative with 256 sets.
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
cache blocks.
– Caches are physically addressed, implement a least recently used (LRU) replacement
algorithm, and are lockable on a cache-block basis.
— MMUs with 32-entry TLB, fully-associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, as well as 8 Mbytes; 16 virtual
address spaces and 16 protection groups
— Advanced on-chip-emulation debug mode
• The MPC885 family provides enhanced ATM functionality as found on the MPC862 and MPC866
Families. The MPC885 family includes the following:
— Improved operation, administration and maintenance (OAM) support
— OAM performance monitoring (PM) support
— Multiple APC priority levels available to support a range of traffic pace requirements
— Port-to-port switching capability without the need for RAM-based microcode
— Simultaneous MII (100Base-T) and UTOPIA (half- or full-duplex) capability
— Optional statistical cell counters per PHY
— UTOPIA-level-2-compliant interface with added FIFO buffering to reduce the total cell
transmission time and Multi-PHY support. (The earlier UTOPIA level-1 specification is also
supported.)
— Parameter RAM for both SPI and I
— Supports full-duplex UTOPIA operation, both master (ATM side) and slave (PHY side), using
a 'split' bus
— AAL2/VBR functionality is ROM-resident
• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
• 32 address lines
1-2
2
C can be relocated without RAM-based microcode
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Table 1-1).
Freescale Semiconductor