Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 837

Powerquicc family

Table of Contents

Character length in bits per character. Must be between 0011 (4 bits) and 1111 (16 bits). A value

less than 4 causes erratic behavior. If the value is not greater than a byte, every byte in memory

holds LEN valid bits. If the value is greater than a byte, every half-word holds LEN valid bits. See

Section 30.4.1.2, "SPI Examples with Different SPMODE[LEN] Values."

Prescale modulus select. Specifies the divide ratio of the prescale divider in the SPI clock generator.

BRGCLK is divided by 4 * ([PM0–PM3] + 1), a range from 4 to 64. The clock has a 50% duty cycle.

SPI Transfers with Different Clocking Modes

shows the SPI transfer format in which SPICLK starts toggling in the middle of the transfer

(SPMODE[CP] = 0).

(From Master)

(From Slave)

Note: Q = Undefined Signal

shows the SPI transfer format in which SPICLK starts toggling at the beginning of the transfer

(SPMODE[CP] = 1).

(From Master)

(From Slave)

Note: Q = Undefined Signal

Freescale Semiconductor

Table 30-1. SPMODE Field Descriptions (continued)

Figure 30-5. SPI Transfer Format with SPMODE[CP] = 0

Figure 30-6. SPI Transfer Format with SPMODE[CP] = 1

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Serial Peripheral Interface (SPI)