Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 177

• An attempt to access memory with an effective address alignment that is invalid for the
instruction causes the alignment exception handler to be invoked. See
"Alignment Exception (0x00600),"
• The execution of an sc instruction invokes the system call exception handler that permits a
program to request the system to perform a service.
• The execution of a trap instruction invokes the program exception trap handler.
Exceptions caused by asynchronous events are described in
5.2.3 Instruction Set Overview
This section provides a brief overview of the instructions implemented in the MPC885 and highlights any
special information with respect to how the MPC885 implements a particular instruction. Note that the
categories used in this section correspond to those used in Chapter 4, "Addressing Modes and Instruction
Set Summary," in The Programming Environments Manual.
Note that some of the instructions have the following optional features:
• CR Update—The dot (.) suffix on the mnemonic enables the update of the CR.
• Overflow option—The 'o' suffix indicates that the XER overflow bit is enabled.
5.2.4 PowerPC UISA Instructions
The PowerPC UISA includes the base user-level instruction set (excluding a few user-level cache control,
synchronization, and time base instructions), user-level registers, programming model, data types, and
addressing modes. This section discusses the instructions defined in the UISA.
5.2.4.1 Integer Instructions
This section describes the integer instructions. These consist of the following:
• Integer arithmetic instructions
• Integer compare instructions
• Integer logical instructions
• Integer rotate and shift instructions
Integer instructions use the content of the GPRs as source operands and place results into GPRs, into the
XER, and into condition register (CR) fields.
5.2.4.1.1 Integer Arithmetic Instructions
Table 5-2 lists the integer arithmetic instructions for the MPC885.
Name
Add Immediate
Add Immediate Shifted
Add
Freescale Semiconductor
for restrictions on operand alignment.
Table 5-2. Integer Arithmetic Instructions
addi
addis
add (add.addo addo.)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Chapter 6, "Exceptions."
Mnemonic
MPC885 Instruction Set
Section 6.1.2.6,
Syntax
rD,rA,SIMM
rD,rA,SIMM
rD,rA,rB
5-7