Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 228

Instruction and Data Caches
4. Repeat steps 2 and 3 to load and lock another cache block.
5. Read DC_CST[CCER2] to determine if the sequence completed without errors.
After the load-and-lock cache block command is written to the DC_CST register, the cache checks if the
block containing the byte addressed by DC_ADR[ADR] is in the cache (hit). If it is in the cache, the block
is locked and the command terminates with no exception. If the block is not in the cache, a normal miss
sequence is initiated (see
block is placed into the cache, the block is locked.
The user must check DC_CST[CCER2] to determine if the load-and-lock cache block operation
completed without error. The error type bits in the DC_CST register are sticky, thus allowing the user to
perform a series of load-and-lock commands before checking the termination status. These bits are set by
the MPC885 and are cleared by software.
Note that the MPC885 considers all zero-wait-state devices on the internal bus as caching-inhibited. For
this reason, software should not perform load-and-lock operations from these devices on the internal bus.
7.3.2.2.3 Data Cache Unlock Cache Block Command
The unlock cache block command (DC_CST[CMD] = 0b1000) is used to unlock previously locked cache
blocks. To unlock a cache block:
1. Write the address of the cache block to be unlocked to the DC_ADR register.
2. Write the unlock cache block command (DC_CST[CMD] = 0b1000) to the DC_CST register.
If the block is found in the cache (hit), it is unlocked and thereafter operates as a regular valid cache block.
If the block is not found in the cache (miss), no operation is performed. There are no error cases for the
unlock block command.
The data cache performs the unlock cache block command in one clock cycle.
7.3.2.2.4 Data Cache Unlock All Command
The data cache unlock all command (DC_CST[CMD] = 0b1010) is used to unlock the entire data cache
with a single command. When the unlock all command is performed, if a cache block is locked, it is
unlocked and thereafter operates as a regular valid cache block. If a block is not locked or if it is marked
invalid, no operation is performed. There are no error cases for the unlock all command.
The data cache performs the unlock all command in one clock cycle.
7.3.2.2.5 Data Cache Invalidate All Command
The data cache invalidate all command (DC_CST[CMD] = 0b1100) causes all unlocked, valid blocks in
the data cache to be marked invalid, regardless of whether the data is modified. Therefore, this command
may effectively destroy modified data. To invalidate the entire data cache the invalidate all command
should be preceded by an unlock all command. Note that the data cache is not automatically invalidated at
hard reset.
As a result of the invalidate all command, the LRU bits of all cache blocks point to either the unlocked
way or to way 0 if both ways are unlocked. There are no error cases for the invalidate all command.
7-16
Section 7.6, "Data Cache Operation,"
MPC885 PowerQUICC Family Reference Manual, Rev. 2
for more information). After the addressed
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