Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 317

Chapter 11
Reset
The reset block has reset control logic that determines the cause of reset, synchronizes it if necessary, and
resets the appropriate logic modules. The memory controller, system protection logic, interrupt controller,
and parallel I/O signals are initialized only on hard reset. Soft reset initializes the internal logic while
maintaining the system configuration. The system configuration includes the SIU pin configuration, the
parallel I/O configuration, and the memory controller configuration.
of the MPC885.
Reset Logic
Reset Source
and PLL
States Reset
Power-on reset Yes
External hard No
reset,
loss-of-lock,
software
watchdog,
checkstop, debug
port hard reset
JTAG reset,
external soft
reset, debug port
soft reset
1
Includes SIU pin configuration, the parallel I/O configuration and the memory controller configuration
2
Includes all other CPM and core logic not explicitly noted elsewhere in the table
11.1 Types of Reset
The MPC885 has several sources of input to the reset logic:
• Power-on reset
• External hard reset
• Internal hard reset
— Software watchdog reset
— Checkstop reset
— Debug port hard reset
• JTAG reset
Freescale Semiconductor
Table 11-1. MPC885 Reset Responses
System Clock
1
Configuration Module
Reset Reset
Yes
No
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Table 11-1
Reset Effect
Debug
HRESET
Port
Driven
Config
Yes Yes Yes
No No
shows the reset responses
Other Internal
SRESET
2
Logic Config
Driven
Reset
Yes Yes
11-1