Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 727

Powerquicc family

Table of Contents

Asynchronous HDLC Mode Parameter RAM

For asynchronous HDLC mode, the protocol-specific area of the SCC parameter RAM is mapped as in

Table 25-1. Asynchronous HDLC-Specific SCC Parameter RAM Memory Map

From SCC base. SCC base = IMMR + 0x3D00 (SCC2) or 0x3E00 (SCC3) or 0x3F00 (SCC4)

shows bit arrangements for TXCTL_TBL and RXCTL_TBL.

0x1F 0x1E 0x1D 0x1C 0x1B 0x1A 0x19

0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09

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CRC constant. Initialize with 0x0000_F0B8.

CRC preset. Initialize with 0x0000_FFFF.

Hword Beginning-of-flag-character. Initialize to PPP-0x7E, IrLAP - 0xC0.

Hword End-of-flag character. Initialize to PPP-0x7E, IrLAP-0xC1.

Hword Control escape character. Initialize to 0x7D for both PPP and IrLAP.

Hword Clear this field.

Hword Reserved

Hword Received frames threshold. Number of Rx frames needed to trigger SCCE[RXF]

Control character tables. Stores the bit array used for the Tx/Rx control characters.

25-3. Each bit corresponds to a character that should be mapped

according to RFC 1549. If a TXCTL_TBL bit is set, its corresponding character is

mapped; otherwise, it is not mapped. If an RXCTL_TBL bit is set, its corresponding

character is discarded if received; otherwise, it is received normally. TXCTL_TBL

and RXCTL_TBL should be initialized to zero for IrLAP.

Hword Number of opening flags to be sent at the beginning of a frame. A value of n

corresponds to n+1 flags.

Hword Reserved

Figure 25-3. TXCTL_TBL/RXCTL_TBL

MPC885 PowerQUICC Family Reference Manual, Rev. 2

SCC Asynchronous HDLC Mode and IrDA