Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 53

Figure
Number
15-15 GPCM-to-SRAM Configuration......................................................................................... 15-19
15-16 GPCM Peripheral Device Interface .................................................................................... 15-21
15-17 GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0) ................................. 15-21
15-18 GPCM Memory Device Interface ....................................................................................... 15-22
15-19 GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, TRLX = 0)....................... 15-22
GPCM Memory Device Basic Timing (ACS ≠ 00, CSNT = 1, TRLX = 0)....................... 15-23
15-20
15-21 GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1) .................... 15-23
15-22 GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0, TRLX = 1) ................... 15-24
15-23 GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 1, TRLX =1) .................... 15-25
15-24 GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX =1) .................... 15-25
15-25 GPCM Read Followed by Write (EHTR = 0)..................................................................... 15-26
15-26 GPCM Read Followed by Write (EHTR = 1)..................................................................... 15-27
15-27 GPCM Read Followed by Read from Different Banks (EHTR = 1) .................................. 15-28
15-28 GPCM Read Followed by Read from Same Bank (EHTR = 1) ......................................... 15-29
15-29 Asynchronous External Master Configuration for
GPCM-Handled Memory Devices ................................................................................. 15-30
15-30 Asynchronous External Master, GPCM-Handled
Memory Access Timing (TRLX = 0)............................................................................. 15-31
15-31 User-Programmable Machine Block Diagram.................................................................... 15-32
15-32 RAM Array Indexing .......................................................................................................... 15-33
15-33 Memory Periodic Timer Request Block Diagram .............................................................. 15-34
15-34 UPM Clock Scheme One (Division Factor = 1) ................................................................. 15-35
15-35 UPM Clock Scheme Two (Division Factor = 2)................................................................. 15-35
15-36 UPM Signals Timing Example One (Division Factor = 1, EBDF = 00) ............................ 15-36
15-37 UPM Signals Timing Example Two (Division Factor = 2, EBDF = 01) ............................ 15-37
15-38 RAM Array and Signal Generation .................................................................................... 15-37
15-39 The RAM Word................................................................................................................... 15-38
15-40 CSx Signal Selection........................................................................................................... 15-42
15-41 BSx Signal Selection........................................................................................................... 15-42
15-42 Early GPL5 Control ............................................................................................................ 15-44
15-43 Address Multiplex Timing .................................................................................................. 15-47
15-44 UPM Read Access Data Sampling...................................................................................... 15-52
15-45 Wait Mechanism Timing for Internal and External Synchronous Masters ......................... 15-53
15-46 Wait Mechanism Timing for an External Asynchronous Master........................................ 15-54
15-47 Synchronous External Master Access................................................................................. 15-57
15-48 Asynchronous External Master Access............................................................................... 15-58
15-49 Synchronous External Master Interconnect Example ......................................................... 15-59
15-50 Synchronous External Master: Burst Read Access to Page Mode DRAM......................... 15-60
15-51 Asynchronous External Master Interconnect Example....................................................... 15-61
15-52 Asynchronous External Master Timing Example ............................................................... 15-62
15-53 Page-Mode DRAM Interface Connection........................................................................... 15-63
Freescale Semiconductor
Figures
Title
MPC885 PowerQUICC Family Reference Manual, Rev. 2
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Number
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