Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 635

Powerquicc family

Table of Contents

There are two definitions of the IDL bus frame structure—8- and 10-bit. The only difference between them

is the channel order within the frame. See

1. Clocks are not to scale.

2. L1RQ x and L1GR x are not shown.

Note that previous versions of Motorola IDL-defined bit functions called auxiliary (A) and maintenance

(M) were removed from the IDL definition when it was concluded that the IDL control channel would be

out-of-band. These functions were defined as a subset of the Motorola SPI format called serial control port

(SCP). To implement the A and M bits as originally defined, program the TSA to access these bits and

route them transparently to an SCC or SMC. Use the SPI to perform out-of-band signaling.

The MPC885 supports all channels of the IDL bus in the basic rate. Each bit in the IDL frame can be routed

to any SCC and SMC or they can assert a strobe output that supports an external device.

The MPC885 supports the request-grant method for contention detection on the D channel of the IDL basic

rate and when the MPC885 has data to send on the D channel, it asserts L1RQx. The physical layer device

monitors the physical layer bus for activity on the D channel and indicates that the channel is free by

asserting L1GRx. The MPC885 samples L1GRx when the IDL sync signal (L1RSYNCx) is asserted. If

L1GRx is asserted, the MPC885 sends the first zero of the opening flag in the first bit of the D channel. If

a collision is detected on the D channel, the physical layer device negates L1GRx. The MPC885 then stops

its transmission and resends the frame when L1GRx is reasserted. This procedure is handled automatically

for the first two buffers of a frame.

For the primary rate IDL, the MPC885 supports up to four 8-bit channels in the frame, determined by the

SI RAM programming. Additionally, the MPC885 can assert strobes to support additional external IDL

channels. The IDL interface supports the CCITT I.460 recommendation for data rate adaptation since it

separately accesses each bit of the IDL bus. The current-route RAM specifies the bits that are supported

by the IDL interface and the serial controller. The receiver accepts only the bits enabled by the Rx route

RAM. Likewise, the transmitter sends only the bits enabled in the Tx route RAM and three-states L1TXDx.

Freescale Semiconductor

Figure 20-26. IDL Bus Signals

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Serial Interface