Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 50

Figure
Number
8-11 IMMU Real Page Number Register (MI_RPN) ................................................................... 8-19
8-12 DMMU Real Page Number Register (MD_RPN) ................................................................ 8-21
8-13 MMU Tablewalk Base Register (M_TWB).......................................................................... 8-22
8-14 MMU Current Address Space ID Register (M_CASID) ...................................................... 8-22
8-15 MMU Access Protection Registers (MI_AP/MD_AP)......................................................... 8-23
8-16 MMU Tablewalk Special Register (M_TW)......................................................................... 8-23
8-17 IMMU CAM Entry Read Register (MI_CAM) .................................................................... 8-24
8-18 IMMU RAM Entry Read Register 0 (MI_RAM0) ............................................................... 8-25
8-19 IMMU RAM Entry Read Register 1 (MI_RAM1) ............................................................... 8-26
8-20 DMMU CAM Entry Read Register (MD_CAM) ................................................................. 8-27
8-21 DMMU RAM Entry Read Register 0 (MD_RAM0) ............................................................ 8-28
8-22 DMMU RAM Entry Read Register 1 (MD_RAM1) ............................................................ 8-29
8-23 DTLB Reload Code Example ............................................................................................... 8-32
8-24 ITLB Reload Code Example................................................................................................. 8-32
8-25 Configuring the TLB Replacement Counter ......................................................................... 8-33
9-1 Data Cache Load Timing ........................................................................................................ 9-1
9-2 Writeback Arbitration Timing—Example 1............................................................................ 9-2
9-3 Writeback Arbitration Timing—Example 2............................................................................ 9-2
9-4 Private Writeback Bus Load Timing....................................................................................... 9-3
9-5 External Load Timing ............................................................................................................. 9-3
9-6 Full Completion Queue Timing .............................................................................................. 9-4
9-7 Branch Folding Timing ........................................................................................................... 9-4
9-8 Branch Prediction Timing ....................................................................................................... 9-5
9-9 Bus Latency for String Instructions ........................................................................................ 9-8
10-1 System Configuration and Protection Logic ......................................................................... 10-3
10-2 Internal Memory Map Register (IMMR) .............................................................................. 10-4
10-3 SIU Module Configuration Register (SIUMCR) .................................................................. 10-5
10-4 System Protection Control Register (SYPCR)...................................................................... 10-7
10-5 Transfer Error Status Register (TESR) ................................................................................. 10-9
10-6 Register Lock Mechanism .................................................................................................. 10-11
10-7 MPC885 Interrupt Structure................................................................................................ 10-12
10-8 SIU Interrupt Processing ..................................................................................................... 10-13
10-9 IRQ0 Logical Representation.............................................................................................. 10-14
10-10 SIU Interrupt Pending Register (SIPEND) ......................................................................... 10-15
10-11 SIU Interrupt Mask Register (SIMASK) ............................................................................ 10-16
10-12 SIU Interrupt Edge/Level Register (SIEL) ......................................................................... 10-17
10-13 SIU Interrupt Vector Register (SIVEC) .............................................................................. 10-18
10-14 Interrupt Table Handling Example...................................................................................... 10-19
10-15 Software Watchdog Timer Service State Diagram.............................................................. 10-20
10-16 Software Watchdog Timer Block Diagram ......................................................................... 10-21
10-17 Software Service Register (SWSR) .................................................................................... 10-21
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Title
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
Freescale Semiconductor