Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 593

19.3.2 IDMA Parameter RAM
Both IDMA channels have a dedicated portion of dual-port RAM for channel parameters.
shows the memory map.
1
Offset Name
0x00 IBASE
0x02 DCMR
0x04 SAPR
0x08 DAPR
0x0C IBPTR
0x0E WRITE_SP
0x10 S_BYTE_C
0x14 D_BYTE_C
0x18 S_STATE
0x1C ITEMP
0x2C SR_MEM
0x30 READ_SP
0x32 —
0x34 —
0x36 —
0x38 D_STATE
Note: Boldfaced items must be initialized by the user before enabling an IDMA channel. The remaining parameters
are used by the CP only.
1
IDMA1 base = IMMR + 0x3CC0
IDMA2 base = IMMR + 0x3DC0
19.3.3 IDMA Registers
Each IDMA channel has a DMA channel mode register (DCMR), an IDMA status register (IDSR) and
corresponding mask register (IDMR) that contain global channel parameters.
Freescale Semiconductor
Table 19-4. IDMA Parameter RAM Memory Map
Width
Hword IDMA BD base address. Defines the base address of the area in dual-port RAM
set aside for this channel's BD table. It is an offset from the beginning of dual-port
RAM. Note that IBASE should be burst-aligned (divisible by 16).
Hword DMA channel mode register. See
Registers (DCMR)."
Word Source data pointer (internal-use). Points to the next source byte to be read.The
CP initializes SAPR to the BD's source buffer pointer and increments it
automatically if the source is memory (DCMR[S/D] = 0bx0).
Word Destination data pointer (internal-use). Points to the next destination byte to be
written. The CP initializes DAPR to the BD's destination buffer pointer, and
increments it automatically if the destination is memory (DCMR[S/D] = 0b0x).
Hword Current IDMA BD pointer. If the IDMA channel is idle, IBPTR points to the next
valid BD in the table. After a reset, or when the end (wrap bit) of the BD table is
reached, the CP wraps IBPTR back to IBASE.
Hword Internal-use
Word Internal source byte count
Word Internal destination byte count
Word Internal state
4 Words Temp data storage
Word Data storage for peripheral write
Hword Internal-use
Hword Difference between source and destination residue
Hword Temp storage address pointer
Hword SR_MEM byte count
Word Reserved. Internal state used by CP
MPC885 PowerQUICC Family Reference Manual, Rev. 2
SDMA Channels and IDMA Emulation
Description
Section 19.3.3.1, "DMA Channel Mode
Table 19-4
19-7