Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 668

Powerquicc family

Table of Contents

Serial Communications Controllers

The DPLL can be driven by one of the baud rate generator outputs or an external clock, CLKx. In the block

diagrams, this clock is labeled HSRCLK/HSTCLK. The HSRCLK/HSTCLK should be approximately 8x,

16x, or 32x the data rate, depending on the coding chosen. The DPLL uses this clock, along with the data

stream, to construct a data clock that can be used as the SCC Rx and/or Tx clock. In all modes, the DPLL

uses the input clock to determine the nominal bit time. If the DPLL is bypassed, HSRCLK/HSTCLK is

used directly as RCLK/TCLK.

At the beginning of operation, the DPLL is in search mode, whereas the first transition resets the internal

DPLL counter and begins DPLL operation. While the counter is counting, the DPLL watches the incoming

data stream for transitions; when one is detected, the DPLL adjusts the count to produce an output clock

that tracks incoming bits.

The DPLL has a carrier-sense signal that indicates when data transfers are on RXD. The carrier-sense

signal asserts as soon as a transition is detected on RXD; it negates after the programmed number of clocks

in GSMR_L[TSNC] when no transitions are detected.

To prevent itself from locking on the wrong edges and to provide fast synchronization, the DPLL should

receive a preamble pattern before it receives the data. In some protocols, the preceding flags or syncs can

function as a preamble; others use the patterns in

generate preamble patterns, as programmed in GSMR_L[TPP, TPL].

Figure 21-14. DPLL Transmitter Block Diagram

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Divided Clock

21-8. When transmission occurs, the SCC can

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