Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 294

System Interface Unit
This register is affected by HRESET but is not affected by SRESET.
Bits Name
0 EARB External arbitration. For more information, see
depends on the reset configuration; see
0 Internal arbitration is performed.
1 External arbitration is assumed.
1–3 EARP External arbitration request priority. Defines the priority of the external master's arbitration request
relative to requests by internal modules. Valid when EARB is cleared. 000 = lowest priority and 111
= highest (however, the internal UPM-based refresh cycles always have a higher priority and will
preempt any external master if the internal arbiter is used). See
4–7 — Reserved, should be cleared.
8 DSHW Data show cycles. Selects the show cycle mode to be applied to data cycles. Data show cycles do
not include CPU interaction with the data cache; they only include CPU interactions with peripherals
on the internal U-bus (that is, CPM and SIU). (Instruction show cycles are programmed in ICTRL
see the Hardware Specifications for more information.) This bit is locked by the DLK bit.
0 Disable show cycles for all internal data cycles.
1 Show address and data of all internal data cycles.
9–10 DBGC Debug pin configuration. The default is set by the hard reset configuration word. See
Section 11.3.1.1, "Hard Reset Configuration Word,"
11–12 DBPC Debug port pins configuration. Determines the active pins for the development port. The default is
set by the hard reset configuration word. See
the description of these bits.
13 — Reserved, should be cleared.
14 FRC FRZ pin configuration. Configures the functionality of FRZ/IRQ6.
0 FRZ/IRQ6 functions as FRZ.
1 FRZ/IRQ6 functions as IRQ6.
15 DLK Debug register lock. If DLK is set, bits 8–15 are locked and writes to those bits are no longer
performed. These bits can be written once the internal FRZ signal is asserted, regardless of the
state of DLK. Cleared at reset.
16-18 — Reserved, should be cleared.
19 MPRE Multiprocessors reservation enable.
0 RSV/IRQ2 functions as IRQ2, and CR/IRQ3 functions as IRQ3.
1 RSV/IRQ2 functions as RSV. The interprocessor reservation protocol is enabled. RSV functions
as defined in
20–21 MLRC Multi-level reservation control. Configures the functionality of KR/RETRY/IRQ4/SPKROUT.
00 KR/RETRY/IRQ4/SPKROUT functions as IRQ4.
01 KR/RETRY/IRQ4/SPKROUT is three-stated.
10 KR/RETRY/IRQ4/SPKROUT functions as KR/RETRY.
11 KR/RETRY/IRQ4/SPKROUT functions as SPKROUT.
22 AEME Asynchronous external master enable. Configures how the memory controller refers to external
asynchronous masters initiating a transaction. If AEME = 1, the memory controller interprets any
assertion of AS as an external asynchronous master initiating a transaction. If it is reset, the memory
controller ignores the value of AS.
10-6
Table 10-3. SIUMCR Field Descriptions
Section 13.4.9, "Memory Reservation."
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Table 10-3
Description
Section 13.4.6, "Arbitration Phase."
Section 11.3.1.1, "Hard Reset Configuration Word."
Figure 13-21
for the description of these bits.
Section 11.3.1.1, "Hard Reset Configuration Word,"
describes SIUMCR fields.
The default value
and Table 19-1.
for
Freescale Semiconductor