Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 618

Powerquicc family

Table of Contents

Serial Interface

(SIRP) register can be used to determine which SI RAM entry is active. In addition, by externally

connecting a strobe to an interrupt signal, an individual SI RAM entry can generate an interrupt.

One TDM Channel with Dynamic Frames

In an SI configuration using one TDM channel with dynamic frames, TDMa has 32 entries apiece for Tx

and Rx data/strobe routing, as shown in

other is shadow RAM that can be safely reprogrammed. After programming the shadow RAM, set the

CSRx bit of the associated channel in the SI command register (SICMR). When the next frame sync

arrives, the SI swaps the current-route RAM with the shadow RAM.

SI RAM Address:

(32-Bit Entries)

Figure 20-8. SI RAM Partitioning Using TDMa with Dynamic Frames

Two TDM Channels with Dynamic Frames

In an SI configuration using both TDM channels with dynamic frames, each channel has 16 entries apiece

for Tx and Rx data/strobe routing, as shown in Figure 20-9. One partition is the current-route RAM; the

other is shadow RAM that can be safely reprogrammed. After programming the shadow RAM, the user

sets SICMR[CSRx]. When the next frame sync arrives, the SI swaps the current-route RAM with the

SI RAM Address:

(32-Bit Entries)

Figure 20-9. SI RAM Partitioning Using Two TDMs with Dynamic Frames

20-8. One RAM partition is the current-route RAM; the

TDMa with Shadow RAM for Dynamic Route Changes

Two Channels with Shadow RAM for Dynamic Route Changes

Framing Signals

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Framing Signals

Framing Signals

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