Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 566

Communications Processor Module and CPM Timers
To implement the same function with a 32-bit timer using timers 1 and 2, follow these steps:
1. Set TGCR = 0x0080. Cascade timers 1 and 2 and put them in reset state.
2. Set TMR2 = 0x001A to set the prescaler to divide by 1 and the clock source to the general system
clock. This value also enables an interrupt when the timer reaches the reference count and
immediately clears the TCN for the next interrupt.
3. Set TMR1 = 0x0000. Enable timer 1 to use the timer 2 output as its input (TMR1[ICLK] = 0b00).
4. Set TCN1 = 0x0000 and TCN2 = 0x0000. Initialize the count of the combined timers 1 and 2 to
zero (TMR1 default) by using one 32-bit data move to TCN1.
5. Set TRR1 = 0x0000 and TRR2 = 0x00FA. Initialize the reference value of the combined timers 1
and 2 to 250 by using one 32-bit data move to TRR1.
6. Write TER2 = 0xFFFF to clear TER2 of any previous events.
7. Set CIMR = 0x0004_0000 to enable timer 2 interrupts in the CPIC and initialize the CICR.
8. Set TGCR = 0x0091 to enable timers 1 and 2 to begin counting in cascaded mode.
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MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor