Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 150

The MPC8xx Core
• Trap instructions
• Logical instructions
• Rotate and shift instructions
Most integer instructions can execute in 1 clock cycle. For details about the performance of the various
instructions, see Table 3-1.
Note the following special cases:
• If an mtspr or mfspr instruction specifies an invalid SPR in which spr[0] = 1, a program exception
occurs if the processor is in user mode. Valid SPRs are listed in
Set."
• If divw[o][.] is used to perform either (0x80000000
are 0x8000_0000 and if Rc = 1, the contents of the bits in the CR field 0 are LT = 1, GT = 0, EQ =
0, and SO is set to the correct value.
• In the cmpi, cmp, cmpli, and cmpl instructions, the L bit is applicable for 64-bit implementations.
For the MPC885, if L = 1 the instruction form is invalid. The core ignores this bit and, therefore,
the behavior when L = 1 is identical to the valid form instruction with L = 0.
3.6.3 Load/Store Unit
The load/store unit (LSU) transfers all data between the GPRs and the processor's internal bus. It is
implemented as an independent execution unit so that stalls in the memory pipeline affect the master
instruction pipeline only if there is a data dependency.
The following lists the LSU's main features:
• All instructions implemented in hardware, including unaligned, string, and multiple accesses
• Two-entry load/store instruction address queue
• Pipelined operation. The LSU pipelines load accesses. Individual cache accesses of all
multiple-register instructions and unaligned accesses are pipelined into the data cache interface.
• Load/store multiple and string instructions synchronize
• Load/store breakpoint/watchpoint detection support
• The LSU implements cache and TLB management instructions as special bus write cycles, which
are issued to the data cache interface.
Figure 3-5 is a block diagram of the LSU and its two queues. The address queue is a 2-entry queue shared
by all load/store instructions and the integer data queue is a 2-entry, 32-bit queue that holds integer data.
The LSU has a dedicated writeback bus so that loaded data received from the internal bus is written
directly back to the GPRs.
3-10
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Chapter 4, "MPC8xx Core Register
÷ ÷
–1) or (<anything> 0), the contents of rD
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