Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 945

Chapter 35
CPM Interrupt Controller
The CPM interrupt controller (CPIC) accepts and prioritizes the internal and external interrupt requests
from the CPM blocks and passes them to the system interface unit (SIU). The CPIC also provides a vector
during the core interrupt acknowledge cycle.
35.1 Features
The following is a list of the CPIC's main features:
• Twenty-nine interrupt sources—17 internal and 12 external (through port C)
• Sources can be assigned to a programmable interrupt level.
• Programmable priority between USB and SCCs
• Two priority schemes for the USB and SCCs
• Programmable highest priority request
• Fully nested interrupt environment
• Individual interrupt sources can be masked in the CPM interrupt mask register (CIMR).
• Unique vector number for each interrupt source
The CPIC manages interrupts from internal CPM sources. These sources are primarily generated by
controllers, such as the USB, SCCs, SMCs, SPI, and I
and port C parallel I/O signals described in
generate interrupts at the same time; therefore, the CIMR register is provided for masking individual
sources. Additional masking is provided for specific interrupt events within each controller that reports
interrupts through the CPIC. These mask registers are described in the chapters that describe individual
controllers. All CPIC-managed interrupt sources are prioritized and bits are set in the CPM interrupt
pending register (CIPR).
Figure 35-1 shows the MPC885 interrupt structure. The left of the figure shows individual interrupt
sources managed by the CPIC, which signals CPIC-managed interrupts to the SIU, shown in the middle
of Figure 35-1. All interrupts signaled by the CPIC are presented to the SIU at a single programmable
priority level (0–7). In turn, the SIU controls which PowerPC architecture-defined external interrupt
exception condition is reported to the MPC8xx core.
For information about the SIU interrupt structure, see
information about the external interrupt exception, see
(0x00500)."
Freescale Semiconductor
Section 34.4, "Port C."
MPC885 PowerQUICC Family Reference Manual, Rev. 2
2
C but also include the 12 general-purpose timers
More than one of these sources may
Section 10.5.1, "Interrupt Structure."
Section 6.1.2.5, "External Interrupt Exception
For
35-1