Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 64

Figure
Number
48-12 MDEU Reset Control Register ........................................................................................... 48-16
48-13 MDEU Status Register........................................................................................................ 48-17
48-14 MDEU Interrupt Status Register ......................................................................................... 48-19
48-15 MDEU Interrupt Control Register ...................................................................................... 48-20
48-16 MDEU EU_GO Register .................................................................................................... 48-22
48-17 MDEU Context Register ..................................................................................................... 48-23
48-18 AESU Mode Register.......................................................................................................... 48-25
48-19 AESU Key Size Register .................................................................................................... 48-27
48-20 AESU Data Size Register ................................................................................................... 48-28
48-21 AESU Reset Control Register............................................................................................. 48-28
48-22 AESU Status Register ......................................................................................................... 48-29
48-23 AESU Interrupt Status Register .......................................................................................... 48-31
48-24 AESU Interrupt Control Register........................................................................................ 48-33
48-25 AESU End of Message Register ......................................................................................... 48-34
48-26 AESU Context Register ...................................................................................................... 48-35
49-1 Example Data Packet Descriptor .......................................................................................... 49-2
49-2 Descriptor Header ................................................................................................................. 49-2
49-3 OP_n sub fields ..................................................................................................................... 49-3
49-4 Descriptor Length Field ........................................................................................................ 49-5
49-5 Descriptor Pointer Field ........................................................................................................ 49-5
49-6 Next Descriptor Pointer Field ............................................................................................... 49-6
49-7 Chain of Descriptors ............................................................................................................. 49-7
50-1 Crypto-Channel Configuration Register ............................................................................... 50-2
50-2 Crypto-Channel Pointer Status Register 1 ............................................................................ 50-5
50-3 Crypto-Channel Pointer Status Register 2 ............................................................................ 50-5
50-4 Crypto-Channel Current Descriptor Pointer Register ......................................................... 50-10
50-5 Fetch Register ..................................................................................................................... 50-11
50-6 Data Packet Descriptor Buffer ............................................................................................ 50-12
51-1 Interrupt Mask Register 1 ..................................................................................................... 51-2
51-2 Interrupt Mask Register 2 ..................................................................................................... 51-2
51-3 Interrupt Status Register 1..................................................................................................... 51-3
51-4 Interrupt Status Register 2..................................................................................................... 51-3
51-5 Interrupt Clear Register 1...................................................................................................... 51-4
51-6 Interrupt Clear Register 2...................................................................................................... 51-5
51-7 ID Register ............................................................................................................................ 51-6
51-8 Master Control Register ........................................................................................................ 51-7
51-9 Master Error Address Register.............................................................................................. 51-7
52-1 CPTR Register....................................................................................................................... 52-1
52-2 Data Alignment Example...................................................................................................... 52-4
53-1 Watchpoints and Breakpoint Support in the Core................................................................. 53-8
53-2 Instruction Support General Structure ................................................................................ 53-11
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Figures
Title
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
Freescale Semiconductor