Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 800

Serial Management Controllers (SMCs)
Table 29-2. SMC UART and Transparent Parameter RAM Memory Map
1
Offset Name Width
0x00 RBASE Hword RxBDs and TxBDs base address. (BD table pointer) Define starting points in the dual-port
0x02 TBASE Hword
0x04 RFCR Byte
0x05 TFCR Byte
0x06 MRBLR Hword Maximum receive buffer length. The most bytes the MPC885 writes to a Rx buffer before
0x08 RSTATE Word
0x0C — Word
0x10 RBPTR Hword RxBD pointer. Points to the next BD for each SMC channel that the receiver transfers data
0x12 — Hword Rx internal byte count.
0x14 — Word
0x18 TSTATE Word
0x1C — Word
0x20 TBPTR Hword TxBD pointer. Points to the next BD for each SMC channel the transmitter transfers data
0x22 — Hword Tx internal byte count.
0x24 — Word
29-6
RAM of the set of BDs for the SMC send and receive functions. They allow flexible
partitioning of the BDs. By selecting RBASE and TBASE entries for all SMCs and by
setting W in the last BD in each list, BDs are allocated for the send and receive side of
every SMC. Initialize these entries before enabling the corresponding channel.
Configuring BD tables of two enabled SMCs to overlap causes erratic operation. RBASE
and TBASE should be a multiple of eight.
Rx/Tx function code. See Section 29.2.3.1, "SMC Function Code Registers
(RFCR/TFCR)."
moving to the next buffer. It can write fewer bytes than MRBLR if a condition like an error
or end-of-frame occurs, but it cannot exceed MRBLR. Rx buffers should not be smaller
than MRBLR. SMC Tx buffers are unaffected by MRBLR.
Tx buffers can be individually given varying lengths through the data length field. MRBLR
can be changed while an SMC is operating only if it is done in a single bus cycle with one
16-bit move (not two 8-bit bus cycles back-to-back). This occurs when the CP shifts
control to the next RxBD, so the change does not take effect immediately. To guarantee
the exact RxBD on which the change occurs, change MRBLR only while the SMC
receiver is disabled. MRBLR should be greater than zero and should be even if character
length exceeds 8 bits.
Rx internal state. Can be used only by the CP.
2
Rx internal data pointer. Updated by the SDMA channels to show the next address in
the buffer to be accessed.
to when it is in idle state, or to the current BD during frame processing. After a reset or
when the end of the BD table is reached, the CP initializes RBPTR to the value in RBASE.
Most applications never need to write RBPTR, but it can be written when the receiver is
disabled or when no receive buffer is in use.
2
A down-count value initialized with the MRBLR value and
decremented with every byte the SDMA channels write.
2
Rx temp. Can be used only by the CP.
Tx internal state. Can be used only by the CP.
2
Tx internal data pointer. Updated by the SDMA channels to show the next address in
the buffer to be accessed.
from when it is in idle state or to the current BD during frame transmission. After reset or
when the end of the table is reached, the CP initializes TBPTR to the TBASE value. Most
applications never need to write TBPTR, but it can be written when the transmitter is
disabled or when no transmit buffer is in use. For instance, after a
command is issued and the frame completes its transmission.
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2
A down-count value initialized with the TxBD data length and
decremented with every byte the SDMA channels read.
2
Tx temp. Can be used only by the CP.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
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