Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 443

Figure 15-1 is a block diagram of the memory controller.
Base Register (BR)
Option Register (OR)
Write-Protect
Logic
Machine Mode Register
(MxMR)
Memory Periodic
Timer
Memory Disable
Timer
WP Error
Memory Command Register (MCR)
Memory Status Register (MSTAT)
Memory Address Register (MAR)
Memory Periodic Timer Prescale
Register (MPTPR)
Freescale Semiconductor
Address [0:16], AT[0:2]
Base Register (BR)
Option Register (OR)
SCY[0:3]
WP
Wait State
RD/WR
Counter
BURST, R/W
UPM Access Request
UPM Access Acknowledge
Enable
Turn-On Disable Timer
UPM Access Request (Command)
UPM Command Done
Figure 15-1. Memory Controller Block Diagram
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Address
Latch
Multiplexer
and
Incrementer
Attributes
Expired
GPCM
Load
UPMA
UPM
or
Arbiter
UPMB
Memory Data Register (MDR)
Memory Controller
BADDR[28:30]
NA and AMX Fields
in RAM Word
CS[0:7]
WE[0:3]
OE
TA
CS[0:7]
BS_x[0:3]
GPLx[0:5]
TA
DLT3 (Internal)
UPWAITx
15-3