Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 911

Powerquicc family

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Initializes all the receive parameters in the PIP parameter RAM to their reset state and should only

be issued when the receiver is disabled.

Forces the PIP controller to close the current RxBD if it is being used and to use the next BD in the

table for subsequent data. No action is taken if the PIP controller is not receiving data.

Handshaking I/O Modes

In either handshaking I/O mode, interlocked or pulsed, the PIP can be configured as a transmitter or

receiver and either the CP or the core can control communications. For CP control, BD and parameter

RAM initialization is required; data is stored in the buffers using the SDMA channels dedicated to SMC2.

For core control, software interrupt routines read and write to the PIP data register (PBDAT).

When the PIP transmits, STBO (PB15) is the STB handshake control signal and STBI (PB14) is the ACK

input. When the PIP receives, it generates ACK on STBO in response to STB on STBI. Note that the PIP

controller overrides bits 15 and 14 in the port B data direction register (PBDIR) and PBDAT corresponding

to STBO and STBI. (The open-drain register PBODR does not apply to PB15 and PB14.)

The following subsections describe interlocked and pulsed handshake modes.

Interlocked Handshake Mode

The interlocked handshake mode provides a fast connection between MPC8xxs and can be used for

P1284-protocol advanced byte mode transfers. To connect MPC8xxs using this interface, connect STBO

from one microprocessor to the STBI of the other and connect the appropriate data signals (either

PB[23–16] or PB[31–16]).

When the PIP is transmitting, the CP loads data into the output latch when it receives a request from the

core to begin transfers. Once data is loaded, STB is asserted after a programmable setup time. When ACK

is sampled as low, data is sent, and STB is negated. STB remains negated until new data is loaded into the

output latch and ACK is negated. When the PIP is receiving, input data is latched when STB is sampled

as low. ACK is asserted and then negated after the data is removed from the input latch.

shows the handshake timing of the interlocked mode.

(Output Ready)

(Input Ready)

Freescale Semiconductor

Table 33-12. PIP Receive CP Commands

Figure 33-11. Interlocked Handshake Mode Timing

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Parallel Interface Port (PIP)

Figure 33-11