Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 414

External Bus Interface
When the MPC885 initiates a burst access, the bus interface only recognizes the RETRY assertion as a
retry termination if it detects it before the slave device acknowledges the first data beat. Note that for burst
transactions, RETRY should be asserted externally only on the first or last beats. Assertion of RETRY on
an intermediate beat may result in erratic operation, including lockup of the MPC885 requiring hard reset.
CLKOUT
BR
BG (Output)
BB
A[0:31]
R/W
TSIZ[0:1]
BURST
TS
Data
TA
BI
RETRY
If a burst access is acknowledged on its first beat with a normal TA, but with BI asserted, the following
single-beat transfers initiated by the MPC885 to complete the 16 byte transfers process the RETRY signal
assertion as a TEA. If the MPC885 initiates non-burst access to a small port size device, the transfer size
of the access is bigger than the slave port size, and the first transfer of this access is terminated normally
by the assertion of TA, then subsequent single-beat transfers, which are initiated by the MPC885 to
complete the access, process the RETRY assertion as a TEA.
13-40
Allow external master
to gain the bus
A
If asserted will cause transfer error
Figure 13-31. Retry on Burst Cycle
MPC885 PowerQUICC Family Reference Manual, Rev. 2
A
Freescale Semiconductor