Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 206

Exceptions
Table 6-15 shows how these registers are set:
Table 6-15. Register Settings after an Instruction TLB Error Exception
Register
SRR0 Set to the EA of the instruction that caused the exception.
SRR1 Note that only one of bits 1, 3, and 4 will be set.
1 1 if the translation of an attempted access is not in the translation tables. Otherwise 0
2 0
3 1 if the fetch access was to guarded memory when MSR[IR] = 1. Otherwise 0
4 1 if the access is not permitted by the protection mechanism; otherwise 0.
11–15 0
Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
MSR IP No change
ME No change
LE Copied from the ILE setting of the interrupted process
Other 0
Some instruction TLB registers are set to a value described in
Execution resumes at offset 0x01300 from the base address indicated by MSR[IP].
6.1.3.5 Data TLB Error Exception (0x014000)
This type of exception occurs as a result of one of the following conditions:
• No EA of a load, store, icbi, dcbz, dcbst, dcbf or dcbi instruction can be translated (either the
segment or page valid bit of this page is cleared in the translation table).
• The access violates memory protection.
• An attempt was made to write to a page with a cleared change bit.
The following registers are set, as shown in
Table 6-16. Register Settings After a Data TLB Error Exception
Register
SRR0 Set to the EA of the instruction that caused the exception.
SRR1 1–4 0
10–15 0
Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
MSR IP No change
ME No change
LE Copied from the ILE setting of the interrupted process
Other 0
6-14
Table 6-16.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Setting
Chapter 8, "Memory Management Unit."
Setting
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