Freescale Semiconductor M54455EVB User Manual

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Freescale Semiconductor

User's Manual

M54455EVB User's Manual

by: Microcontroller Solutions Group

Introduction

1.1

Purpose

This document provides design and usage information

for the Freescale M54455EVB evaluation, development

and reference platform.

The M54455EVB platform provides an evaluation

system for the Freescale MCF5445x ColdFire

embedded microprocessor family. The MCF54455 is the

superset device in the family and is the processor

featured on this platform. This allows evaluation and

development for the entire family on a single hardware

platform.

1.2

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Summary of Contents for Freescale Semiconductor M54455EVB

Page 1: Table Of Contents
MCF54455 Overview......2 M54455EVB Overview ..... . 4 Memory Map Overview .
Page 2: Overview
DDR2 SDRAM Specification (JESD79-2C) Overview MCF54455 Overview The MCF54455 is the host processor for the M54455EVB. Figure 1 shows a top-level block diagram of the MCF54455 superset device. The following is a brief summary of the functional blocks in the MCF54455 superset device.
Page 3 – Fast Ethernet Controller – Real time clock GPIO – General Purpose Input/Output – Synchronous Serial Interface – Inter-Integrated Circuit USB OTG – Universal Serial Bus On-the-Go controller Figure 1. MCF54455 Block Diagram M54455EVB User’s Manual, Rev. 4 Freescale Semiconductor...
Page 4: M54455Evb Overview
M54455EVB Overview The M54455EVB provides hardware to evaluate as many of the configurations of the MCF5445x family as possible. The M54455EVB features: • Freescale MCF54455 ColdFire microprocessor • DDR2 SDRAM (256 MByte) • Two NOR flash memory devices (16 MByte, 512 KByte) •...
Page 5 ATA_DATA[15:8] ATA_DATA[15:8] 16MB Flash 8-bit data bus Flash1 Dual FEC PHY (RMII mode) and 2xRJ45 w/ USB ULPI ATX Power Supply integrated magnetics and Interface LEDs MC34702 MC34702 Barrel Pwr Connector 3.3V 1.8V 1.5V 1.2V Figure 3. M54455EVB Block Diagram...
Page 6: Memory Map Overview
Memory Map Overview Figure 1 illustrates the overall memory map for the MCF54455 and M54455EVB. Table 1. M54455EVB Memory Map Function Start Address End Address Size Flexbus—Flash1 0x0000_0000 0x00FF_FFFF 16 MB Flexbus—Flash0 0x0400_0000 0x0407_FFFF 512 KB Flexbus—CPLD 0x0800_0000 0x08FF_FFFF 16 MB Flexbus—FPGA/MRAM...
Page 7: I/O Back Panel
This section describes how to setup the evaluation board to access the bootloader to start Linux. The default communication interface with the M54455EVB is a simple serial port console. A terminal emulator on a host PC and the supplied serial cable is required to interact with the serial port. Alternately, a USB cable can be used if the USB serial port is configured for use (refer to Section 4.17, “Serial...
Page 8: Hardware Submodules
9. The demo application prints out a banner message including the IP address that it obtained from the DHCP server. Launch a web client (e.g. Firefox or Internet Explorer) and copy this IP address into the web browser. The M54455EVB serves up a web page with more information on the available demos.
Page 9: Ddr Sdram Interface
CPLD for test purposes only. These signals are disabled in the normal functional mode. Reset Controller The reset controller on the M54455EVB is implemented in a Xilinx XC95144XL CPLD. The CPLD controls the state of the system reset signal (SYSRESET) gathers reset information from a pushbutton reset (SW2), the BDM interface, and the FPGA (FPGA_DONE).
Page 10 If the BOOTMOD pins are 10 during reset, the MCF5445x configuration after reset is determined according to the levels driven onto the FB_AD[7:0] pins. On the M54455EVB, the FB_AD[7:0] pins are actively driven by an 8-bit buffer enabled when the MCF5445x RSTOUT signal is asserted. The values driven by the buffer are set by the SW3 DIP switch settings.
Page 11 = 8 x f = 16 x f = 6 x f (none) = 12 x f = 18 x f = 24 x f = 10 x f = 20 x f M54455EVB User’s Manual, Rev. 4 Freescale Semiconductor...
Page 12: System Clocks
Configuration Module” chapters of the MCF54455 Reference Manual for more details. System Clocks A single Cypress CY22393 device generates all of the clock signals on the M54455EVB. Alternatively, you can supply the clock signals using external SMA connectors for test purposes. The different clock signals and configurations are described below.
Page 13 C to generate a 60MHz clock signal. There is a provision on the M54455EVB for clocking the MCF5445x with a 25MHz crystal instead of the 33/66MHz external clock. A cut-trace (CT11) can be modified to route the provided 25MHz crystal oscillator circuit to the EXTAL input.
Page 14: Spi Flash
Flash The M54455EVB features two flash devices connected to the FlexBus expansion bus. The smaller of the two flashes is a 512KByte, 8-bit wide AT49BV040 (or compatible) device referred to as Flash0. This device contains the U-Boot bootloader. The larger of the two flashes is a 16 MByte, 8-bit wide 28F128J3D (or compatible) device referred to as Flash1.
Page 15: Pci
The M54455EVB is designed to support 33- and 66-MHz 32-bit PCI cards. However, the speed of the PCI clocks and input clock is limited to that of the slowest device by logic on the M54455EVB. The frequency of these clocks is controlled by an input (S2) into the clock generator logic. The FPGA automatically adjusts this control signal based on the M66EN signal from each PCI slot.
Page 16 PCI arbitration signals to the FPGA. It would then be left to you to implement an external arbitration scheme in the FPGA. The following figures describe how to alter the M54455EVB to route the PCI arbitration signals to the FPGA. Reference designators for the cut-trace board footprints are CT1-CT10. CT1-CT2, CT5-CT7 and CT9 can be found near the PCI slots (J14, J15, J16, J17), and CT8, CT10, CT3 and CT4 can be found near the MCF5445x (U1).
Page 17 Figure 7. PCI Request 1 and Request 2 Cut Trace Option—Use FPGA for Arbitration Figure 8. PCI Request 3 Cut Trace Option—Use FPGA for Arbitration M54455EVB User’s Manual, Rev. 4 Freescale Semiconductor...
Page 18 Figure 9. PCI Grant 0 Cut Trace Option—Use FPGA for Arbitration Figure 10. PCI Grant 1 Cut Trace Option—Use FPGA for Arbitration M54455EVB User’s Manual, Rev. 4 Freescale Semiconductor...
Page 19: Audio
For accessibility ease, all the SSI signals from the MCF5445x are brought to a header, J910. Table 9. SSI Signals on J910 Signal Name Pin Pin Signal Name SSI_RXD SSI_TXD SSI_MCLK SSI_BCLK SSI_FS M54455EVB User’s Manual, Rev. 4 Freescale Semiconductor...
Page 20: Bdm And Jtag
The primary debug port on the MCF5445x is referred to as the background debug module or BDM. The standard 26-pin BDM header (J24) is provided on the M54455EVB for attachment of an external BDM control interface. However, the M54455EVB also features a built-in P&E USB ColdFire Multilink. This interface is brought out to the I/O back panel to a standard Type-B USB receptacle.
Page 21: Usb
4.10.2 ULPI PHY The ULPI interface of the MCF5445x is also featured on the M54455EVB. An external ULPI physical layer device, the SMSC USB3300 (U927), connects directly to the MCF5445x ULPI interface. The USB signals from the ULPI PHY are brought out to a mini-AB USB connector. The ID pin on the mini-AB connector connects to the ULPI PHY’s ID pin and indicates whether a host or device is connected.
Page 22: Ata
4.13 FPGA The M54455EVB FPGA is a Xilinx Spartan 3 FPGA that provides interrupt control for the four PCI slots and the pushbuttons SW6 and SW7. It also provides a buffered FlexBus interface to the external 256K × 16bit MRAM and an interface to a seven-segment display and two LEDs.
Page 23 Indicates the SW6_b signal is asserted. This bit shows the status of the interrupt, even if FPGA_IRQEN[SW6] is cleared. 3–0 Indicates the corresponding interrupt PCI_IRQ line is asserted. These bits show the status of interrupt, even if the corresponding FPGA_IRQEN[PCI] bit is cleared. M54455EVB User’s Manual, Rev. 4 Freescale Semiconductor...
Page 24 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 Figure 15. FPGA IRQROUTE Register Table 16. FPGA_IRQROUTE Field Descriptions Field Description 31–6 Reserved, must be cleared. 5–4 SW7 IRQ selection (pushbutton) 00 IRQ1 01 IRQ3 10 IRQ4 11 IRQ7 M54455EVB User’s Manual, Rev. 4 Freescale Semiconductor...
Page 25 Major revision number. MAJOR_REV Example: Revision 1.2 of the FPGA code. MAJOR_REV = 0x01, MINOR_REV = 0x02 7–0 Minor revision number. MINOR_REV Example: Revision 1.2 of the FPGA code. MAJOR_REV = 0x01, MINOR_REV = 0x02 M54455EVB User’s Manual, Rev. 4 Freescale Semiconductor...
Page 26: Cpld
Controls the state of FPGA_LED1. FPGA_LED1 is reference designator D957. LED1 0 Off 1 On 4.14 CPLD A Xilinx XC95144XL CPLD performs a number of tasks on the M54455EVB including: • Reset control • Boot mode selection • Peripheral multiplexing and enable/disable control •...
Page 27 The CPLD outputs several signals to enable, disable, and control signal routing to and from several peripherals on the M54455EVB. The state of these signals is controllable via a bank of eight DIP switches (SW1) and a Flexbus-accessible memory-mapped register, CPLD_CONTROL. The CPLD_MODE register reflects the value of the switches at reset.
Page 28 ATA interface, the FEC1 interface must be disabled. The MCF5445x provides pin assignment control to route the proper integrated peripheral signals to the external pins. The M54455EVB provides this switch and a programmable bit in the CPLD_CONTROL register to select the appropriate board level routing.
Page 29 4.14.2 M54455EVB Revision Optionally populated resistors on the M54455EVB allow the revision to be indicated at the time of assembly. These resistors connections input to the CPLD, and the values can be read from CPLD_VERSION register. Refer to the description of the CPLD registers below.
Page 30 7–4 Reserved 3–0 Board version. This field reflects the current M54455EVB revision. The value here is the one less than the current BRDVER version of the board (e.g. CPLD_BRDVER of 0x01 indicates M54455EVB Rev 2). M54455EVB User’s Manual, Rev. 4...
Page 31 7–2 Reserved, must be cleared. 1–0 Control state of the corresponding DDR SDRAM on-die termination pins. These pins are for test purposes only. The M54455EVB provides external parallel termination for the DDR2 interface. M54455EVB User’s Manual, Rev. 4 Freescale Semiconductor...
Page 32 Table 32. CPLD_FLASHCFG Field Descriptions Field Description 7–1 Reserved, must be cleared. Flash1 write-protect. This bit controls the state of the FLASH1_WP signal FLASH_WP 0 Flash1 is write-protected 1 Flash1 is not write-protected M54455EVB User’s Manual, Rev. 4 Freescale Semiconductor...
Page 33: Interrupts
The MCF5445x contains a few serial interfaces and timers that are not made available via dedicated interfaces on the M54455EVB. However, these interfaces (and others) are brought out to a general purpose header, J908, for easy access. The following interfaces are accessible on J908: •...
Page 34: Serial Ports
4.17 Serial Ports The MCF5445x includes three UART modules. The M54455EVB provides two standard RS232 line drivers on UART0 and UART1, connected to a dual, stacked DB9 serial port connector (male). The RS232 null-modem cable provided in the kit can connect the serial ports to a host PC.
Page 35: Logic Analyzer Connections
4.18 Logic Analyzer Connections The M54455EVB provides 12 Tektronix P6860 compression connections for use with TLA7Axx logic analyzer modules. These probes allow you to probe Flexbus, PCI and DDR2 signals. See the M54455EVB schematics for more details. 4.19 Power Regulation The M54455EVB provides two Freescale QuiccSupply MC34702 power regulators.
Page 36 Table 36. Interface Headers Reference Designator Function System power indicator for case LED Board reset header for case switch Power ON/OFF for case switch ATA activity indicator for case LED FPGA program header M54455EVB User’s Manual, Rev. 4 Freescale Semiconductor...
Page 37: U-Boot
FPGA_CFG switch. Not used at this time FPGA interrupt pushbutton 0. FPGA interrupt pushbutton 1. U-Boot The M54455EVB comes pre-programmed with the U-Boot bootloader in the boot flash device, Flash0. U-Boot is an open source bootloader with some debugging capabilities. Please refer to http://www.denx.de/wiki/UBoot for documentation.
Page 38 Freescale Semiconductor, Inc. Freescale Semiconductor assume any liability arising out of the application or use of any Technical Information Center, EL516 product or circuit, and specifically disclaims any and all liability, including without 2100 East Elliot Road limitation consequential or incidental damages.