Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1207

ADSP-SC58x ACM Register Descriptions
Missed Event Status Register
The register indicates which enabled event is missed for a particular trigger cycle. When a
ACM_MEVSTAT
ACM_MEVSTAT register bit is set (=1), this status indicates a miss of the corresponding event. This status generates
an interrupt if the corresponding bit in the
EV15 (R/W1C)
Event 15 Missed
EV14 (R/W1C)
Event 14 Missed
EV13 (R/W1C)
Event 13 Missed
EV12 (R/W1C)
Event 12 Missed
EV11 (R/W1C)
Event 11 Missed
EV10 (R/W1C)
Event 10 Missed
EV9 (R/W1C)
Event 9 Missed
EV8 (R/W1C)
Event 8 Missed
Figure 24-22: ACM_MEVSTAT Register Diagram
Table 24-13: ACM_MEVSTAT Register Fields
Bit No.
(Access)
15 EV15
(R/W1C)
24–40
ACM_MEVMSK
15 14 13 12 11
0 0 0 0 0
31 30 29 28 27
0 0 0 0 0
Bit Name
Event 15 Missed.
The ACM_MEVSTAT.EV15 bit indicates a miss of event 15 since the last trigger. If
set and the corresponding bit in
tion generates an interrupt. This bit is W1C.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register is set.
10 9 8 7 6 5 4 3
0 0 0 0 0 0 0 0
26 25 24 23 22 21 20 19
0 0 0 0 0 0 0 0
Description/Enumeration
ACM_MEVMSK
0 No Event 15 Missed Status
1 Event 15 Missed
2 1 0
0 0 0
EV0 (R/W1C)
Event 0 Missed
EV1 (R/W1C)
Event 1 Missed
EV2 (R/W1C)
Event 2 Missed
EV3 (R/W1C)
Event 3 Missed
EV4 (R/W1C)
Event 4 Missed
EV5 (R/W1C)
Event 5 Missed
EV6 (R/W1C)
Event 6 Missed
EV7 (R/W1C)
Event 7 Missed
18 17 16
0 0 0
is set (interrupt enabled), the condi-