Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1198

Event Complete Status Register
The register identifies which enabled event has occurred for a particular trigger cycle. When an
ACM_EVSTAT
ACM_EVSTAT bit is cleared (=0), this status indicates that the ACM has not begun or completed conversion for the
corresponding event (conversion not done). When an
ACM has completed conversion for the corresponding event (conversion done).
EV15 (R/W1C)
Event 15 Status
EV14 (R/W1C)
Event 14 Status
EV13 (R/W1C)
Event 13 Status
EV12 (R/W1C)
Event 12 Status
EV11 (R/W1C)
Event 11 Status
EV10 (R/W1C)
Event 10 Status
EV9 (R/W1C)
Event 9 Status
EV8 (R/W1C)
Event 8 Status
ECOM1S (R/W1C)
Event Complete 1 Status
Figure 24-19: ACM_EVSTAT Register Diagram
Table 24-10: ACM_EVSTAT Register Fields
Bit No.
(Access)
17 ECOM1S
(R/W1C)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15 14 13 12 11 10
0 0 0 0 0 0
31 30 29 28 27 26
0 0 0 0 0 0
Bit Name
Event Complete 1 Status.
The ACM_EVSTAT.ECOM1S bit indicates the state of the ACM_STAT.ECOM1 bit.
If set and the corresponding bit in
tion generates an interrupt. This bit is W1C and is not cleared by a trigger.
ACM_EVSTAT bit is set (=1), this status indicates that the
9 8 7 6 5 4 3 2
0 0 0 0 0 0 0 0
25 24 23 22 21 20 19 18
0 0 0 0 0 0 0 0
Description/Enumeration
ACM_EVMSK
0 No Status
1 ACM_STAT.ECOM1 =1 Occurred
ADSP-SC58x ACM Register Descriptions
1 0
0 0
EV0 (R/W1C)
Event 0 Status
EV1 (R/W1C)
Event 1 Status
EV2 (R/W1C)
Event 2 Status
EV3 (R/W1C)
Event 3 Status
EV4 (R/W1C)
Event 4 Status
EV5 (R/W1C)
Event 5 Status
EV6 (R/W1C)
Event 6 Status
EV7 (R/W1C)
Event 7 Status
17 16
0 0
ECOM0S (R/W1C)
Event Complete 0 Status
is set (interrupt enabled), the condi-
24–31