Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1213

ADSP-SC58x ACM Register Descriptions
Timing Configuration 0 Register
The register determines the frequency of ACM_CLK (using the ACM_TC0.CKDIV field) and the setup
ACM_TC0
cycles (using the ACM_TC0.SC field) for the ADC controls. Setup cycles are specified in terms of SCLK0_0.
Figure 24-24: ACM_TC0 Register Diagram
Table 24-15: ACM_TC0 Register Fields
Bit No.
(Access)
27:16 SC
(R/W)
7:0 CKDIV
(R/W)
24–46
15 14 13
0 0 0
CKDIV (R/W)
Clock Divisor
31 30 29
0 0 0
SC (R/W)
Setup Cycle
Bit Name
Setup Cycle.
The ACM_TC0.SC bits select the ADC control pins and the setup time in SCLK0_0
cycles with respect to the ADC chip select active edge. The setup time may be calculat-
ed from:
Setup Time = ACM_TC0.SC + 1.
The maximum setup cycle time is 4096 * SCLK0_0, and the minimum setup cycle
time is 1 SCLK0_0.
Clock Divisor.
The ACM_TC0.CKDIV bits select the frequency of ACM_CLK as a function of the
system clock frequency (SCLK0_0) and the value of the CKDIV field according to the
formula:
ACM_CLK frequency = (SCLK0_0 frequency)/(ACM_TC0.CKDIV + 1)
The maximum ACM_CLK frequency is SCLK0_0/2, and the minimum ACM_CLK
frequency is SCLK0_0/256. For example, for a 100 MHz SCLK0_0, the ACM_CLK
frequency range is from 390 KHz to 50 MHz.
The value ACM_TC0.CKDIV =0 is reserved.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
12 11 10 9 8 7 6 5
0 0 0 0 0 0 0 0
28 27 26 25 24 23 22 21
0 0 0 0 0 0 0 0
Description/Enumeration
0 1 SCLK0_0 Cycle Setup Time
1 2 SCLK0_0 Cycles Setup Time
4095 4096 SCLK0_0 Cycles Setup Time
4 3 2 1 0
0 0 0 0 1
20 19 18 17 16
0 0 0 0 0