Table 24-13: ACM_MEVSTAT Register Fields (Continued)
Bit No.
(Access)
14
EV14
(R/W1C)
13
EV13
(R/W1C)
12
EV12
(R/W1C)
11
EV11
(R/W1C)
10
EV10
(R/W1C)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Event 14 Missed.
The ACM_MEVSTAT.EV14 bit indicates a miss of event 14 since the last trigger. If
set and the corresponding bit in
tion generates an interrupt. This bit is W1C.
Event 13 Missed.
The ACM_MEVSTAT.EV13 bit indicates a miss of event 13 since the last trigger. If
set and the corresponding bit in
tion generates an interrupt. This bit is W1C.
Event 12 Missed.
The ACM_MEVSTAT.EV12 bit indicates a miss of event 12 since the last trigger. If
set and the corresponding bit in
tion generates an interrupt. This bit is W1C.
Event 11 Missed.
The ACM_MEVSTAT.EV11 bit indicates a miss of event 11 since the last trigger. If
set and the corresponding bit in
tion generates an interrupt. This bit is W1C.
Event 10 Missed.
The ACM_MEVSTAT.EV10 bit indicates a miss of event 10 since the last trigger. If
set and the corresponding bit in
tion generates an interrupt. This bit is W1C.
ADSP-SC58x ACM Register Descriptions
Description/Enumeration
ACM_MEVMSK
is set (interrupt enabled), the condi-
0 No Event 14 Missed Status
1 Event 14 Missed
is set (interrupt enabled), the condi-
ACM_MEVMSK
0 No Event 13 Missed Status
1 Event 13 Missed
ACM_MEVMSK
is set (interrupt enabled), the condi-
0 No Event 12 Missed Status
1 Event 12 Missed
ACM_MEVMSK
is set (interrupt enabled), the condi-
0 No Event 11 Missed Status
1 Event 11 Missed
ACM_MEVMSK
is set (interrupt enabled), the condi-
0 No Event 10 Missed Status
1 Event 10 Missed
24–41
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