Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1232

CAN Operating Modes
In addition to this fundamental rule, CAN_TIMING.TSEG2 must also be greater than or equal to the information
processing time (IPT). IPT is the time required by the logic to sample the CAN_RX input, which is 3 system clock
cycles.
Therefore, restrictions apply to the minimal value of CAN_TIMING.TSEG2 if CAN_CLK.BRP is less than 2. If
CAN_CLK.BRP is set to 0, the CAN_TIMING.TSEG2 field must be greater than or equal to 2. If
CAN_CLK.BRP is set to 1, the minimum CAN_TIMING.TSEG2 value is 1.
Use the same nominal bit rate for all nodes on a CAN bus.
NOTE:
With all the timing parameters set, the final consideration is sampling performance. The default behavior of the
CAN controller is to sample the CAN bit once. The controller samples at the point described by the
register and controlled by the CAN_TIMING.SAM bit. If this bit is set, however, the input signal is oversampled
three times at the system clock rate. The resulting value is generated by a majority decision of the three sample val-
ues. Always keep the CAN_TIMING.SAM bit cleared if the BRP value is less than 4.
Do not modify the CAN_CLK
mode first. Writes to these registers have no effect when CAN is not in configuration or debug mode. If not coming
out of processor reset, enter configuration mode by setting the CAN_CTL.CCR bit and poll the
ter until CAN_STAT.CCA is set.
NOTE: If the CAN_TIMING.TSEG1 field is programmed to 0, the module does not leave the configuration
mode.
During configuration mode, the module is not active on the CAN bus line. The CAN_TX output pin remains reces-
sive and the module does not receive or transmit messages or error frames. After leaving the configuration mode, all
CAN internal core registers and the CAN error counters are set to their initial values.
A soft reset does not change the values of
the CAN bus cannot be corrupted by changing the bit timing parameter or initiating the soft reset (by setting the
CAN_CTL.SRS bit).
CAN Low Power Features
The CAN module includes built-in sleep and suspend modes to save power.
The following sections describe the behavior of the CAN module in these modes.
Built-In Suspend Mode
The most modest of power savings mode is the suspend mode. This mode is entered by setting the CAN_CTL.CSR
bit. The module enters the suspend mode after the current operation of the CAN bus finishes. Then, the internal
logic sets the CAN_STAT.CSA bit. Once CAN enters this mode, the module is no longer active on the CAN bus
line, slightly reducing power consumption.
In suspend mode, the CAN_TX output pin remains in a recessive state, and the module does not receive or transmit
messages or error frames. The content of the
suspend mode.
25–16
and CAN_TIMING registers during normal operation. Always enter configuration
CAN_CLK and CAN_TIMING. Therefore, an ongoing transfer through
CAN_CEC
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register remains unchanged. Clear CAN_CTL.CSR to exit
CAN_TIMING
regis-
CAN_STAT