Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1237

the node postpones the transmission if the received and transmitted bits do not match. However, after the arbi-
tration phase, a bit error is signaled any time the value on CAN_RX does not equal what is transmitted on the
CAN_TX pin. (The arbitration phase completes when the CAN_MB[nn]_ID1.RTR bit is sent successfully.)
• Form error. Occurs when a fixed-form bit position in the CAN frame contains one or more illegal bits. Occurs
when a dominant bit is detected at a delimiter or end of frame bit position.
• Acknowledge error. Occurs whenever a message is sent and no receivers drive an acknowledge bit.
• CRC error. Occurs whenever a receiver calculates the CRC on the data it received and finds it different than
the CRC that transmitted on the bus itself.
• Stuff error. The CAN specification requires the transmitter to insert an extra stuff bit of opposite value after 5
bits have transmitted with the same value. The receiver disregards the value of the stuff bits. However, it takes
advantage of the signal edge to resynchronize itself. A stuff error occurs on receiving nodes whenever the sixth
consecutive bit value is the same as the previous 5 bits.
Once the CAN module detects any of the errors, it updates the
the standard errors, the CAN_ESR.SAO flag signals when the CAN_RX pin sticks at dominant level, indicating a
possibility of shorted wires.
Error Frames
It is important that all nodes on the CAN bus ignore data frames that any single node failed to receive. Every node
sends an error frame as soon as it has detected an error as shown in the CAN Error Example figure.
A device that has detected an error still completes the ongoing bit. It initiates an error frame by sending six domi-
nant and eight recessive bits to the bus. Since this activity is a violation of the bit stuffing rule, all nodes are signaled
to discard the ongoing frame. (All receivers that did not detect the transmission error in the first instance now detect
a stuff bit error.)
The transmitter can detect a normal bit error sooner. It aborts the transmission of the ongoing frame and tries re-
sending it later.
When all nodes on the bus have detected the error, they also send six dominant and eight recessive bits to the bus.
The resulting error frame consists of two different fields. The first field is the superposition of error flags contributed
from the different stations, which are a sequence of 6–12 dominant bits. The second field is the error delimiter and
consists of eight recessive bits indicating the end of frame.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
CAN_ESR and CAN_CEC
CAN Warnings and Errors
registers. In addition to
25–21