Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1241

Sharc+ processor
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Table 25-6: Common CAN Test Mode Bit Combinations (Continued)
MRB
MAA
DIL
1
0
1
1
1
1
1
1
0
1
1
0
1
1
0
ADSP-SC58x CAN Register Descriptions
Controller Area Network (CAN) contains the following registers.
Table 25-7: ADSP-SC58x CAN Register List
Name
CAN_AA1
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DTO
DRI
CDE
0
0
1
0
0
1
0
0
1
0
1
1
1
1
1
Description
Abort Acknowledge 1 Register
Functional Description
Normal transmission on CAN bus line.
Read back.
External acknowledge from external device required.
Normal transmission on CAN bus line.
Read back.
No external acknowledge required.
Transmit message and acknowledge are transmitted on CAN bus line.
CAN_RX input is enabled.
Normal transmission on CAN bus line.
Read back.
No external acknowledge required.
Transmit message and acknowledge transmit on CAN bus line.
CAN_RX input and internal loop are enabled (internal OR of TX and
RX)
Normal transmission on CAN bus line.
Read back.
No external acknowledge required.
Transmit message and acknowledge are transmitted on CAN bus line.
CAN_RX input is ignored.
Internal loop is enabled.
No transmission on CAN bus line.
Read back.
No external acknowledge required.
Nether transmit message nor acknowledge are transmitted on
CAN_TX.
CAN_RX input is ignored.
Internal loop is enabled.
ADSP-SC58x CAN Register Descriptions
25–25

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