Notes To Prevent Malfunctions In Synchronous Clearing For Complementary Pwm Mode - Renesas RX100 Series User Manual

RX13T Group
19.6.25 Notes to Prevent Malfunctions in Synchronous Clearing for Complementary
PWM Mode
If control of the output waveform is enabled (TWCRA.WRE bit = 1) at the time of synchronous counter clearing in
complementary PWM mode, satisfaction of either condition 1 or 2 below has the following effects.
 Dead time on the PWM output pins is shortened (or disappears).
 The active level is output on the negative phase PWM output pins beyond the period for active-level output.
Condition 1: In portion (10) of the initial output inhibition period in Figure 19.138 , synchronous clearing occurs within
the dead-time period for PWM output.
Condition 2: In portions (10) and (11) of the initial output inhibition period in Figure 19.139 , synchronous clearing
occurs when any condition from among MTU3.TGRB ≤ TDDRA, MTU4.TGRA ≤ TDDRA, or
MTU4.TGRB ≤ TDDRA is satisfied.
The following method avoids the above phenomena.
Ensure that synchronous clearing proceeds with the value of each comparison register (MTU3.TGRB, MTU4.TGRA,
and MTU4.TGRB) set to at least double the value of the TDDRA register.
MTU3.TGRA
TGR
TDDR
0
PWM output
(positive phase)
PWM output
(negative phase)
Figure 19.138 Example of Synchronous Clearing (When Condition 1 Applies)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
11
10
MTU3.
TCNT
Tb interval
MTU4.
TCNT
TDDRA
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
Synchronous clearing
10
Dead time is shortened.
: Dead time
Note: PWM output is active low.
11
Tb interval
Initial output
inhibition
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