Access To I/O Registers; Notes On Access To I/O Registers; Data Arrangement; Data Arrangement In Registers - Renesas RX100 Series User Manual

RX13T Group
2.5.2

Access to I/O Registers

The addresses of I/O registers are fixed, and this is regardless of whether the setting is for little endian or big endian.
Accordingly, changes to the endian do not affect access to I/O registers. For the arrangements of I/O registers, refer to the
descriptions of registers in the relevant sections.
2.5.3

Notes on Access to I/O Registers

Ensure that access to I/O registers is in accord with the following rules.
 With I/O registers for which a bus width of 8 bits is indicated, use instructions having operands of the same width (8
bits). That is, access these registers by using instructions with .B as the size specifier (.size), or with .B or .UB as the
size-extension specifier (.memex).
 With I/O registers for which a bus width of 16 bits is indicated, use instructions having operands of the same width
(16 bits). That is, access these registers by using instructions with .W as the size specifier (.size), or with .W or .UW
as the size-extension specifier (.memex).
 With I/O registers for which a bus width of 32 bits is indicated, use instructions having operands of the same width
(32 bits). That is, access these registers by using instructions with .L as the size specifier (.size), or with .L size-
extension specifier (.memex).
2.5.4

Data Arrangement

2.5.4.1

Data Arrangement in Registers

Figure 2.2 shows the relation between the sizes of registers and bit numbers.
Byte (8-bit) data
Word (16-bit) data
Longword (32-bit) data
Figure 2.2 Data Arrangement in Registers
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b15
b31
MSB
2. CPU
b7 b0
b0
b0
LSB
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