Renesas RX100 Series User Manual page 688

RX13T Group
Initialization
Start of reception
Simultaneously set the SIMR3.IICSTAREQ bit
to 1 and the SIMR3.IICSCLS[1:0] and
IICSDAS[1:0] bits to 01b
STI interrupt?
Set the SIMR3.IICSTIF to 0, and set the
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] bits to
Write the slave address and value for
the R/W bit to TDR
TXI interrupt?
SISR.IICACKR = 0?
Set SIMR2.IICACKT to 0
Set SCR.RIE to 1
Next data is the last?
Write FFh as dummy data to TDR
RXI interrupt?
Read received data from RDR
TXI interrupt?
2
Note: In simple I C mode, the TXI interrupt request is generated when
communication is completed, unlike the timing during clock-
synchronous transmission.
Figure 23.55 Example of the Procedure for Master Reception Operations in Simple I
(with Transmission Interrupts and Reception Interrupts in Use)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
No
Yes
00b
No
Yes
No
Yes
Yes
No
No
Yes
No
Yes
23. Serial Communications Interface (SCIg, SCIh)
[ 1 ]
[ 1 ] Initialization for simple I
Set the RIE bit in SCR to 0.
[ 2 ] Generate a start condition.
[ 3 ] Writing to TDR:
Writing the slave address and value for the R/W bit to
[ 2 ]
TDR.
[ 4 ] Confirming ACK response from the slave address:
Check the SISR.IICACKR bit. If its value is 0, it is indicated
that the slave device responded with ACK and operations
proceed. If its value is 1, it is indicated that there was no
response from a slave device so the next transition is to
generation of the stop condition.
[ 5 ] Steps for continuing with reception:
To proceed with reception, write FFh as dummy transmit
data to TDR. Other than in the first and last rounds of
[ 3 ]
transmission, a TXI request can activate DTC to handle
writing of data to TDR. Furthermore, other than for the last
data to be received, an RXI request can activate the DTC
to handle reading of data from RDR.
[ 6 ] NACK is transmitted in response to the last data.
[ 7 ] Generation of a stop condition.
[ 4 ]
[ 5 ]
Set SIMR2.IICACKT to 1
Write FFh as dummy data to TDR
RXI interrupt?
Read received data from RDR
TXI interrupt?
Simultaneously set the SIMR3.IICSTPREQ
bit to 1 and the SIMR3.IICSCLS[1:0] and
IICSDAS[1:0] bits to 01b
STI interrupt?
Set the SIMR3.IICSTIF flag to 0, and set the
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] bits to
2
C mode:
No
Yes
No
Yes
No
Yes
11b
End
2
C Mode
Page 688 of 1041
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