Operation; Periodic Count Operation; Cmcnt Count Timing - Renesas RX100 Series User Manual

RX13T Group
21.3

Operation

21.3.1

Periodic Count Operation

When an frequency dividing clock is selected by the CMCR.CKS[1:0] bits and the CMSTR0.STRn (n = 0, 1) bit is set to
1, the CMCNT counter starts counting up using the selected clock.
When the value in the counter and the value in the register match, a compare match interrupt (CMIn) (n = 0,1) is
generated. The CMCNT counter then starts counting up again from 0000h. Figure 21.2 shows the operation of the
CMCNT counter.
CMCNT value
CMCOR
0000h
Figure 21.2 CMCNT Counter Operation
21.3.2

CMCNT Count Timing

As the count clock to be input to the CMCNT counter, one of four frequency dividing clocks (PCLK/8, PCLK/32, PCLK/
128, and PCLK/512) obtained by dividing the peripheral module clock (PCLK) can be selected with the
CMCR.CKS[1:0] bits. Figure 21.3 shows the timing of the CMCNT counter.
Count clock
CMCNT
Figure 21.3 CMCNT Count Timing
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Counter cleared by compare match with CMCOR
PCLK
PCLK/ i-1 clocks
N - 1
i = 8, 32, 128, or 512
21. Compare Match Timer (CMT)
N
Time
N + 1
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