Renesas RX100 Series User Manual page 325

32-bit mcu
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RX13T Group
I/O pins
MTU3
: MTIOC3A
MTIOC3B
MTIOC3C
MTIOC3D
MTU4
: MTIOC4A
MTIOC4B
MTIOC4C
MTIOC4D
Clock input
Internal clock:
PCLKB
PCLKB/2
PCLKB/4
PCLKB/8
PCLKB/16
PCLKB/32
PCLKB/64
PCLKB/256
PCLKB/1024
External clock: MTCLKA
MTCLKB
MTCLKC
MTCLKD
MTIOC1A
I/O pins
MTU0: MTIOC0A
MTIOC0B
MTIOC0C
MTIOC0D
MTU1: MTIOC1A
MTIOC1B
MTU2: MTIOC2A
MTIOC2B
Internal pins
MTU5: MTIC5U
MTIC5V
MTIC5W
TCR:
Timer control register
TCR2:
Timer control register 2
TCRU:
Timer control register U
TCR2U:
Timer control register 2U
TCRV:
Timer control register V
TCR2V:
Timer control register 2V
TCRW:
Timer control register W
TCR2W:
Timer control register 2W
TMDR1:
Timer mode register 1
TMDR2A:
Timer mode register 2
TMDR3:
Timer mode register 3
TIOR:
Timer I/O control register
TIORH:
Timer I/O control register H
TIORL:
Timer I/O control register L
TIORU:
Timer I/O control register U
TIORV:
Timer I/O control register V
TIORW:
Timer I/O control register W
TIER:
Timer interrupt enable register
TIER2:
Timer interrupt enable register 2
TSR:
Timer status register
TBTM:
Timer buffer operation transfer mode
register
Figure 19.1
Block Diagram of MTU (MTU0 to MTU5)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
TCNT:
Timer counter
TCNTLW:
Timer longword counter
TGRA:
Timer general register A
TGRALW:
Timer longword general register A
TGRB:
Timer general register B
TGRBLW:
Timer longword general register B
TGRC:
Timer general register C
TGRD:
Timer general register D
TGRE:
Timer general register E
TGRF:
Timer general register F
TSTRA:
Timer start register
TSYRA:
Timer synchronous register
TCSYSTR:
Timer counter synchronous start register
TRWERA:
Timer read/write enable register
TOERA:
Timer output master enable register
TOCR1A:
Timer output control register 1
TOCR2A:
Timer output control register 2
TOLBRA:
Timer output level buffer register
TGCRA:
Timer gate control register A
TCNTSA:
Timer subcounter
TCDRA:
Timer period data register
TCBRA:
Timer period buffer register
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
Interrupt request signals
MTU3: TGIA3
TGIB3
TGIC3
TGID3
TCIV3
MTU4: TGIA4
TGIB4
TGIC4
TGID4
TCIV4
Internal peripheral bus
A/D converter start signal
TRG4AN, TRG4BN
TRG4ABN
skipping control logic
A/D conversion start
A/D conversion start
request frame
request frame
synchronization
synchronization signal
signal generation
Interrupt request signals
MTU0: TGIA0
TGIB0
TGIC0
TGID0
TGIE0
TGIF0
TCIV0
MTU1: TGIA1
TGIB1
TCIV1
TCIU1
MTU2: TGIA2
TGIB2
TCIV2
TCIU2
Interrupt request signals
MTU5: TGIU5
TGIV5
TGIW5
TDDRA:
Timer dead time data register
TDERA:
Timer dead time enable register
TBTERA:
Timer buffer transfer set register
TWCRA:
Timer waveform control register
TICCR:
Timer input capture control register
TADCR:
Timer A/D converter start request
control register
TADCORA:
Timer A/D converter start request
cycle set register A
TADCORB:
Timer A/D converter start request
cycle set register B
TADCOBRA: Timer A/D converter start request
cycle set buffer register A
TADCOBRB: Timer A/D converter start request
cycle set buffer register B
TITMRA:
Timer interrupt skipping mode register
TITCR1A:
Timer interrupt skipping set register 1
TITCR2A:
Timer interrupt skipping set register 2
TITCNT1A:
Timer interrupt skipping counter 1
TITCNT2A:
Timer interrupt skipping counter 2
NFCRn:
Noise filter control register n
ADSM0
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