Timer Interrupt Skipping Counter 1 (Titcnt1A) - Renesas RX100 Series User Manual

RX13T Group
19.2.39

Timer Interrupt Skipping Counter 1 (TITCNT1A)

Address(es): MTU.TITCNT1A 0009 5231h
b7 b6
—
Value after reset: 0 0
Bit Symbol
b2 to b0 T4VCNT[2:0]
b3 —
b6 to b4 T3ACNT[2:0]
b7 —
Note: To clear the TITCNT1A, set the TITCR1A.T3AEN and TITCR1A.T4VEN bits to 0.
TITCNT1A is 8-bit readable/writable counters. TITCNT1A retains their values even after stopping the count operation
of MTU3.TCNT and MTU4.TCNT.
T4VCNT[2:0] Bits (TCIV4 Interrupt Counter)
[Clearing conditions]
 When the TITM bit in TITMRA is 1
 When the T4VEN bit in TITCR1A is set to 0
 When the T4VCOR[2:0] bits in TITCR1A are set to 000b
 When the T4VCNT[2:0] bits in TITCNT1A match the T4VCOR[2:0] bits in TITCR1A
T3ACNT[2:0] Bits (TGIA3 Interrupt Counter)
[Clearing conditions]
 When the TITM bit in TITMRA is 1
 When the T3AEN bit in TITCR1A is set to 0
 When the T3ACOR[2:0] bits in TITCR1A are set to 000b
 When the T3ACNT[2:0] bits in TITCNT1A match the T3ACOR[2:0] bits in TITCR1A
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
T3ACNT[2:0] —
0 0 0 0
Bit Name
TCIV4 Interrupt Counter
Reserved
TGIA3 Interrupt Counter
Reserved
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b1 b0
T4VCNT[2:0]
0 0
Description
While the T4VEN bit in TITCR1A is set to 1, the count in these
bits is incremented every time a TCIV4 interrupt occurs.
This bit is read as 0.
While the T3AEN bit in TITCR1A is set to 1, the count in these
bits is incremented every time a TGIA3 interrupt occurs.
This bit is read as 0.
R/W
R
R
R
R
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