Renesas RX100 Series User Manual page 432

32-bit mcu
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RX13T Group
(g) PWM Period Setting
In complementary PWM mode, the PWM period is set in two registers—MTU3.TGRA, in which the MTU3.TCNT
upper limit value is set, and TCDRA, in which the MTU4.TCNT upper limit value is set. The settings should be made so
as to achieve the following relationship between these two registers:
With dead time: MTU3.TGRA setting = TCDRA setting + TDDRA setting
Without dead time: MTU3.TGRA setting = TCDRA setting + 1
In addition, the settings should be made so as to achieve the following relationship between the TCDRA register and the
TDDRA register:
TCDRA setting > TDDRA setting × 2 + 2
The MTU3.TGRA and TCDRA settings are made by setting values in buffer registers MTU3.TGRC and TCBRA. When
data is written to MTU4.TGRD to enable transfers, the values set in MTU3.TGRC and TCBRA are transferred
simultaneously to the MTU3.TGRA and TCDRA with the transfer timing selected with the MTU3.TMDR1.MD[3:0]
bits.
The new PWM period is reflected from the next cycle when data is updated at the crest, or from the current cycle when
updated in the trough. Figure 19.49 illustrates the operation when the PWM period is updated at the crest.
Refer to the following section, (h), Register Data Updating , for the method of updating the data in each buffer register.
MTU3.TCNT
MTU4.TCNT
TCNTSA
Counter value
MTU3.TGRA
Figure 19.49
Example of PWM Period Updating (MTU3 and MTU4)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
MTU3.TGRC
MTU3.TGRA
update
update
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
MTU3.TCNT
MTU4.TCNT
Time
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