Generation Of Start, Restart, And Stop Conditions - Renesas RX100 Series User Manual

RX13T Group
23.7.1

Generation of Start, Restart, and Stop Conditions

Writing 1 to the IICSTAREQ bit in the SIMR3 register causes the generation of a start condition. The generation of a
start condition proceeds through the following operations.
 The level on the SSDAn line falls (from the high level to the low level) and the SSCLn line is kept in the released
state.
 The hold time for the start condition is secured as half of a bit period at the bit rate determined by the setting of the
BRR.
 The level on the SSCLn line falls (from the high level to the low level), the IICSTAREQ bit in the SIMR3 register
is set (to 0), and a start-condition generated interrupt is output.
Writing 1 to the IICRSTAREQ bit in the SIMR3 register causes the generation of a start condition. The generation of a
start condition proceeds through the following operations.
 The SSDAn line is released and the SSCLn line is kept at the low level.
 The period at low level for the SSCLn line is secured as half of a bit period at the bit rate determined by the setting
of the BRR.
 The SSCLn line is released (transition from the low to the high level).
 Once the high level on the SSCLn line is detected, the setup time for the restart condition is secured as half of a bit
period at the bit rate determined by the setting of the BRR.
 The level on the SSDAn line falls (from the high level to the low level).
 The hold time for the restart condition is secured as half of a bit period at the bit rate determined by the setting of the
BRR.
 The level on the SSCLn line falls (from the high level to the low level), the IICRSTAREQ bit in the SIMR3 register
is set (to 0), and a restart-condition generated interrupt is output.
Writing 1 to the IICSTPREQ bit in the SIMR3 register causes the generation of a stop condition. The generation of a stop
condition proceeds through the following operations.
 The level on the SSDAn line falls (from the high level to the low level) and the SSCLn line is kept at the low level.
 The period at low level for the SSCLn line is secured as half of a bit period at the bit rate determined by the setting
of the BRR.
 The SSCLn line is released (transition from the low to the high level).
 Once the high level on the SSCLn line is detected, the setup time for the stop condition is secured as half of a bit
period at the bit rate determined by the setting of the BRR.
 The SSDAn is released (transition from the low to the high level), the IICSTPREQ bit in the SIMR3 register is set
(to 0), and a stop-condition generated interrupt is output.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
23. Serial Communications Interface (SCIg, SCIh)
Page 680 of 1041