Cascaded Operation - Renesas RX100 Series User Manual

RX13T Group
19.3.4

Cascaded Operation

In cascaded operation, two 16-bit counters in different channels are used together as a 32-bit counter.
There are two functions for connecting MTU1 and MTU2 to use as a 32-bit counter: cascade connection to be set when
the MTU1.TMDR3.LWA bit is 0, and cascade connection 32-bit phase counting mode to be set when the
MTU1.TMDR3.LWA bit is 1. For details on cascade connection 32-bit phase counting mode, refer to section 19.3.6.2,
Cascade Connection 32-Bit Phase Counting Mode . This section describes the cascade connection function to be set
when the MTU1.TMDR3.LWA bit is 0.
This function operates when the MTU1.TMDR3.LWA bit is set to 0 and the MTU1.TCR.TPSC[2:0] bits are set so that
MTU1.TCNT counts at an overflow/underflow of MTU2.TCNT. Underflow occurs only when the MTU2 to which the
lower 16 bits allocated is in phase counting mode.
Table 19.47 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for MTU1, the count clock setting is invalid and the counters operate
independently in phase counting mode.
Table 19.47 Cascaded Combinations
Combination
MTU1 and MTU2
For simultaneous input capture of MTU1.TCNT and MTU2.TCNT during cascaded operation, additional input capture
input pins can be specified by the input capture control register (TICCR). The input-capture condition is of edges in the
signal produced by taking the logical OR of the input level on the main input pin and the input level on the added input
pin. Accordingly, if either is at the high level, a change in the level of the other will not produce an edge for detection.
For details, refer to (4), Cascaded Operation Example (c) . For input capture in cascade connection, refer to section
19.6.21, Simultaneous Input Capture in MTU1.TCNT and MTU2.TCNT in Cascade Connection .
Table 19.48 shows the TICCR setting and input capture input pins.
Table 19.48 TICCR Setting and Input Capture Input Pins
Target Input Capture
Input capture from MTU1.TCNT to
MTU1.TGRA
Input capture from MTU1.TCNT to
MTU1.TGRB
Input capture from MTU2.TCNT to
MTU2.TGRA
Input capture from MTU2.TCNT to
MTU2.TGRB
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Upper 16 Bits
MTU1.TCNT
TICCR Setting
I2AE bit = 0 (Initial value)
I2AE bit = 1
I2BE bit = 0 (Initial value)
I2BE bit = 1
I1AE bit = 0 (Initial value)
I1AE bit = 1
I1BE bit = 0 (Initial value)
I1BE bit = 1
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
Lower 16 Bits
MTU2.TCNT
Input Capture Input Pin
MTIOC1A
MTIOC1A, MTIOC2A
MTIOC1B
MTIOC1B, MTIOC2B
MTIOC2A
MTIOC2A, MTIOC1A
MTIOC2B
MTIOC2B, MTIOC1B
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