Renesas RX100 Series User Manual page 18

19.6.19 Note on Transition from Normal Mode or PWM Mode 1
to Reset-Synchronized PWM Mode ......................................................................................... 494
19.6.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode ............ 494
19.6.21 Simultaneous Input Capture in MTU1.TCNT and MTU2.TCNT in Cascade Connection ...... 494
19.6.22 Interrupt Skipping Function 2 ................................................................................................... 495
19.6.23 Notes When Complementary PWM Mode Output Protection Function is Not Used .............. 495
19.6.24 Notes Regarding Timer Counter (MTU5.TCNT) and Timer General Register (MTU5.TGR) 495
19.6.25 Notes to Prevent Malfunctions in Synchronous Clearing for Complementary PWM Mode ... 496
19.6.26 Continuous Output of Interrupt Signal in Response to a Compare Match ............................... 498
19.6.27 Usage Notes on A/D Converter Delaying Function in Complementary PWM Mode ............. 498
19.7 MTU Output Pin Initialization .......................................................................................................... 500
19.7.1 Operating Modes ...................................................................................................................... 500
19.7.2 Operation in Case of Re-Setting Due to Error during Operation ............................................. 500
19.7.3 Overview of Initialization Procedures and Mode Transitions
in Case of Error during Operation ............................................................................................ 501
20. Port Output Enable 3 (POE3C) .................................................................................................... 527
20.1 Overview ........................................................................................................................................... 527
20.2 Register Descriptions ......................................................................................................................... 530
20.2.1 Input Level Control/Status Register 1 (ICSR1) ........................................................................ 530
20.2.2 Input Level Control/Status Register 3 (ICSR3) ........................................................................ 531
20.2.3 Input Level Control/Status Register 4 (ICSR4) ........................................................................ 532
20.2.4 Input Level Control/Status Register 6 (ICSR6) ........................................................................ 533
20.2.5 Output Level Control/Status Register 1 (OCSR1) ................................................................... 534
20.2.6 Active Level Setting Register 1 (ALR1) .................................................................................. 535
20.2.7 Software Port Output Enable Register (SPOER) ..................................................................... 537
20.2.8 Port Output Enable Control Register 1 (POECR1) .................................................................. 538
20.2.9 Port Output Enable Control Register 2 (POECR2) .................................................................. 540
20.2.10 Port Output Enable Control Register 4 (POECR4) .................................................................. 541
20.2.11 Port Output Enable Control Register 5 (POECR5) .................................................................. 542
20.2.12 Port Output Enable Comparator Output Detection Flag Register (POECMPFR) .................... 543
20.2.13 Port Output Enable Comparator Request Select Register (POECMPSEL) ............................. 544
20.3 Operation ........................................................................................................................................... 545
20.3.1 Input-Level Detection Operation .............................................................................................. 551
Output-Level Compare Operation ............................................................................................ 552
20.3.2
20.3.3 High-Impedance Control Using Registers ................................................................................ 553
20.3.4 High-Impedance Control through Detection of Oscillation Stop ............................................. 553
20.3.5 High-Impedance Control through Detection of the Comparator Output .................................. 553
20.3.6 Additional Functions for High-Impedance Control .................................................................. 553
20.3.7 Recover from High-Impedance State ....................................................................................... 553
20.4 POE Setting Procedure ...................................................................................................................... 555
20.5 Interrupts ............................................................................................................................................ 555
20.6 Usage Notes ....................................................................................................................................... 556