Digital Filter For Input On The Rxdx12 Pin - Renesas RX100 Series User Manual

RX13T Group
23.10.5

Digital Filter for Input on the RXDX12 Pin

Signals input through the RXDX12 pin can be passed through a digital filter before they are conveyed to the internal
circuits. The digital filter consists of three flip-flop circuit stages connected in series and a match-detecting circuit. The
CR2.DFCS[2:0] bits select the sampling clock for the RXDX12 pin input signals. If the outputs of all three latches
match, the given level is conveyed to subsequent circuits. If the levels do not match, the previous value is retained. In
other words, levels are confirmed as being the signal if they are retained for at least three cycles of the sampling clock but
judged to be noise rather than changes in the signal level if they change within three cycles of the sampling clock. Figure
23.69 shows an example of operations with the digital filter.
CR2.DFCS[2:0]
Base clock
PCLK/8
PCLK/16
PCLK/32
PCLK/64
PCLK/128
RXDX12 input
signal
RXDX12 input signal
RXDX12 input signal after
passing through the digital filter
Figure 23.69 Example of Operations with the Digital Filter
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Sampling clock
C C
D Q D
Clock period selected by
DFCS[2:0]
Sampling clock
Change in signal level is not recognized
due to not matching 3 times.
23. Serial Communications Interface (SCIg, SCIh)
C
Q D Q
Delay in signal propagation:
up to 3 sampling-clock cycles
Match-
detection
circuit
Page 705 of 1041