Renesas RX100 Series User Manual page 731

RX13T Group
TRS Bit (Transmit/Receive Mode)
This bit indicates transmit or receive mode.
The RIIC is in receive mode when the TRS bit is set to 0 and is in transmit mode when the bit is set to 1. Combination of
this bit and the MST bit indicates the operating mode of the RIIC.
The value of TRS bit is automatically changed to 1 for transmit mode or 0 for receive mode by issuing or detection of a
start condition and setting of the R/W# bit. Although writing to the TRS bit is possible when the ICMR1.MTWP bit is set
to 1, writing to this bit is not necessary during normal usage.
[Setting conditions]
 When a start condition is issued normally according to the start condition issuance request (when a start condition is
detected with the ST bit set to 1)
 When a restart condition is issued normally according to the restart condition issuance request (when a restart
condition is detected with the RS bit set to 1)
 When the R/W# bit added to the slave address is set to 0 in master mode
 When the address received in slave mode matches the address enabled in the ICSER register, with the R/W# bit set
to 1
 When 1 is written to the TRS bit with the ICMR1.MTWP bit set to 1
[Clearing conditions]
 When a stop condition is detected
 The ICSR2.AL (arbitration-lost) flag being set to 1
 In master mode, reception of a slave address to which an R/W# bit with the value 1 is appended
 In slave mode, a match between the received address and the address enabled in the ICSER register when the value
of the received R/W# bit is 0 (including cases where the received address is the general call address)
 In slave mode, a restart condition is detected (a start condition is detected with ICCR2.BBSY flag is 1 and
ICCR2.MST bit is 0)
 When 0 is written to the TRS bit with the ICMR1.MTWP bit set to 1
 When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset
MST Bit (Master/Slave Mode)
This bit indicates master or slave mode.
The RIIC is in slave mode when the MST bit is set to 0 and is in master mode when the bit is set to 1. Combination of this
bit and the TRS bit indicates the operating mode of the RIIC.
The value of the MST bit is automatically changed to 1 for master mode or 0 for slave mode by issuing of a start
condition and issuing or detection of a stop condition, etc. Although writing to the MST bit is possible when the
ICMR1.MTWP bit is set to 1, writing to this bit is not necessary during normal usage.
[Setting conditions]
 When a start condition is issued normally according to the start condition issuance request (when a start condition is
detected with the ST bit set to 1)
 When 1 is written to the MST bit with the ICMR1.MTWP bit set to 1
[Clearing conditions]
 When a stop condition is detected
 When the ICSR2.AL (arbitration-lost) flag is set to 1
 When 0 is written to the MST bit with the ICMR1.MTWP bit set to 1
 When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
2
24. I C-bus Interface (RIICa)
Page 731 of 1041